Multi-Level Flash Memory LDPC Interleaving for Signal Separation
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Solution Overview
Problem
The challenge in multi-level flash memory is the reduced signal distance between adjacent levels, making it difficult to discern signal levels and limiting the number of signal levels that can be written into each cell, resulting in uncertainty and overlap in signal distributions.
Innovation Solution
A memory apparatus utilizing a low-density parity check (LDPC) coder and bit-interleaved code modulation (BICM) with a constellation map based on Gray code, combined with pulse amplitude modulation (PAM), to encode and decode multi-level signals, enhancing data reliability and density by reducing overlap between signal levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level signals are used to increase memory capacity, then data density is improved, but signal distance between adjacent levels deteriorates
Solution Approach 1:
The signal is segmented into multiple levels (4-level signaling) where each level represents a distinct voltage threshold. By dividing the signal range into discrete segments, the system achieves higher data density (2 bits per cell) while maintaining distinguishable levels through careful threshold placement, thus resolving the contradiction between increased density and maintained signal distance.
Solution Approach 2:
The system changes the voltage parameter distribution by using distinct threshold levels (Vth0, Vth1, Vth2, Vth3) with optimized spacing. The parameter transformation involves mapping 2-bit data values to specific voltage levels with sufficient margin between adjacent levels, allowing high density while preserving measurement precision through parameter optimization.
2Quantity of substance
If more signal levels are written into each cell, then data density is improved, but signal level distinction deteriorates
Solution Approach 1:
The system performs preliminary actions by pre-defining distinct threshold levels and voltage distributions before writing data. The programming process prepares the memory cell with reference levels that are established in advance, making it easier to distinguish between different signal levels during reading operations, thus reducing detection difficulty while maintaining high density.
Solution Approach 2:
The patent introduces threshold voltage levels as intermediary reference points between adjacent signal levels. These intermediary thresholds act as decision boundaries that facilitate clear distinction between signal levels, enabling reliable detection of 4-level signals even when adjacent levels are closely spaced, thus resolving the contradiction between high density and easy detection.
3Quantity of substance
If four signal levels are used per cell, then data density is improved, but signal level uncertainty increases
Solution Approach 1:
The system applies beforehand cushioning by introducing voltage margins and threshold guards between adjacent signal levels. The programming and reading operations incorporate cushioning voltages that prevent overlap between probability distributions of adjacent levels, reducing uncertainty and improving reliability while maintaining 4-level signaling for high data density.
Solution Approach 2:
The patent implements feedback mechanisms through read-verify-program cycles where the system reads the programmed signal level, compares it against threshold levels, and adjusts programming if the signal falls outside the acceptable range. This feedback loop reduces signal level uncertainty by ensuring each programmed level falls within the correct threshold boundaries, thereby improving reliability while maintaining high data density.
Data Source
AI summary
Embodiments of the present invention provide multi-level signal memory with LDPC and interleaving. Thus, various embodiments of the present invention provide a memory apparatus that includes a memory block comprising a plurality of memory cells, each memory cell adapted to operate with multi-level signals. Such a memory apparatus also includes a low density parity check (LDPC) coder to LDPC code data values to be written into the memory cells and an interleaver adapted to apply bit interleaved code modulation (BICM) to the LDPC coded data values to generate BICM coded data values. Other embodiments may be described and claimed.