Flash Memory Leakage-Inhibition Layers for Voltage Retention Trade-off
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Solution Overview
Problem
Conventional flash memory cells face challenges in scaling down write/erase voltages while maintaining ten-year data retention, as reducing the thickness of tunneling oxide layers leads to charge leakage and increased voltages are required to prevent leakage, conflicting with the need for data retention.
Innovation Solution
Incorporating leakage-inhibition layers between the tunneling and storage layers and between the blocking and gate electrodes, with specific conduction band alignments and materials like silicon nitride and high-k dielectrics, to reduce charge leakage and allow for lower write/erase voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the thickness of tunneling oxide layer is decreased to reduce write/erase voltages, then write/erase voltages are lowered, but charge leakage increases and data retention deteriorates
Solution Approach 1:
The patent segments the tunneling oxide layer into multiple thinner oxide layers separated by nitride layers. This segmentation allows each oxide layer to be thin enough to enable low-voltage operation while the nitride interlayers prevent charge leakage paths, thereby maintaining data retention reliability despite reduced individual oxide thickness
Solution Approach 2:
The nitride layers serve as intermediary elements between the tunneling oxide layers. These nitride interlayers act as charge trapping layers that intercept and trap charges, preventing them from leaking through the thin oxide layers, thus enabling both low write/erase voltages and reliable data retention
2Reliability
If the thickness of blocking oxide layer is increased to prevent charge leakage, then data retention is improved, but write/erase voltages must be increased
Solution Approach 1:
The blocking oxide layer is segmented into multiple thinner oxide layers separated by nitride layers. This segmentation allows the total blocking thickness to be sufficient for preventing charge leakage and ensuring data retention, while each individual oxide layer remains thin enough to be penetrated at lower voltages during write/erase operations
Solution Approach 2:
Different regions of the blocking structure have different local qualities: the nitride layers provide high charge trapping capability at specific locations, while the oxide layers provide insulation. This local differentiation allows the blocking structure to prevent charge leakage effectively while enabling low-voltage operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves reduced leakage, prolonged data retention, and lower write/erase voltages, enhancing the performance of flash memory cells by minimizing charge loss and optimizing voltage requirements.
Implementation Method 1
The first leakage-inhibition layer is between the tunneling layer and the storage layer, and has a fourth conduction band lower than the first conduction band
Implementation Method 2
The second leakage-inhibition layer is between the blocking layer and the gate electrode, and has a fifth conduction band lower than the third conduction band
Implementation Method 3
Each of the memory cells can be electrically charged by injecting electrons from the drain region through the tunneling oxide layer into the floating gate
Data Source
AI summary
A semiconductor device includes a semiconductor substrate; a tunneling layer over the semiconductor substrate, wherein the tunneling layer has a first conduction band; a storage layer over the tunneling layer, wherein the storage layer has a second conduction band; a blocking layer over the storage layer, wherein the blocking layer has a third conduction band; a gate electrode over the blocking layer; and at least one of a first leakage-inhibition layer and a second leakage-inhibition layer. The first leakage-inhibition layer is between the tunneling layer and the storage layer, and has a fourth conduction band lower than the first conduction band. The second leakage-inhibition layer is between the blocking layer and the gate electrode, and has a fifth conduction band lower than the third conduction band.