Flash Memory Leakage Current Prevention via Terminal Equalization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory cells experience leakage current during the erasing process due to over-erasure of neighboring cells, affecting normal operation and requiring labor-intensive and time-consuming programming adjustments.
Innovation Solution
Connecting the first and second terminals of neighboring memory cells through a metal line to equalize voltage levels, forming a circuit loop that minimizes leakage current and ensures normal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If source side erasing technology is used to erase the left bit of the boundary memory cell, then the erasing process is efficient, but the right bit of the neighboring memory cell is over-erased causing leakage current
Solution Approach 1:
The patent applies preliminary anti-action by programming the right bit of the neighboring memory cell to a high level voltage either before or after erasing the left bit of the boundary memory cell. This preemptive measure creates a protective voltage barrier that counteracts the harmful over-erasing effect before it can cause leakage current, while still allowing the efficient source side erasing process to proceed.
2Object-generated harmful factors
If the right bit of the neighboring memory cell is programmed to high level voltage to prevent leakage current, then leakage current is reduced, but the processing time and complexity increase
Solution Approach 1:
The patent merges the leakage prevention operation with the existing erasing and programming workflows. By integrating the high-level voltage programming of the neighboring cell's right bit into the normal memory operation sequence, the solution prevents leakage current without requiring separate dedicated processing steps, thus minimizing additional time consumption.
3Object-generated harmful factors
If programming is applied to each row of flash memory to prevent leakage current, then leakage current is reduced, but the process becomes labor-consuming and time-intensive
Solution Approach 1:
The patent establishes a universal solution that can be applied across all rows of the flash memory array using the same methodology. The technique of programming the right bit of neighboring cells to high level voltage serves multiple functions: it prevents leakage current, protects boundary cells, and maintains memory integrity, all through a standardized approach that reduces overall processing complexity.
Data Source
AI summary
A method for preventing a memory from generating a leakage current is disclosed. The memory includes a boundary memory cell and a neighboring memory cell. The neighboring memory cell is adjacent to the boundary memory cell. The method includes the following step. The first terminal of the neighboring memory cell is connected to the second terminal through a metal line.