Flash Memory Voltage Control for Leakage Reduction
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Solution Overview
Problem
Flash memory devices face challenges in efficient erasing and programming operations due to high voltage differences that can cause tunneling effects and lead to leakage currents and device deterioration.
Innovation Solution
A flash memory device design that includes a voltage control unit to compare and apply a lower voltage to selection lines during erasing, preventing voltage exceeding the bulk region voltage, and a programming method that applies specific voltages to dummy and normal word lines to reduce voltage differences and minimize leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high voltage is applied to the bulk region during erasing operation, then the erasing efficiency is improved, but the voltage difference between selection lines and bulk region causes tunneling effects and leakage currents
Solution Approach 1:
The voltage control unit dynamically adjusts the selection line voltage based on the bulk region voltage level. During erasing operation, when the bulk region voltage is increased to improve erasing efficiency, the voltage control unit correspondingly increases the selection line voltage to maintain an appropriate voltage difference, thereby preventing tunneling effects and leakage currents while preserving the improved erasing efficiency
Solution Approach 2:
The invention changes the voltage parameter of the selection lines adaptively based on the bulk region voltage state. By using the voltage control unit to monitor and adjust the selection line voltage in response to bulk region voltage changes, the system optimizes the voltage difference parameter to prevent harmful tunneling effects while maintaining effective erasing operation
2Productivity
If a high voltage is applied to the bulk region during erasing operation, then the erasing efficiency is improved, but the device deterioration is caused by excessive voltage differences
Solution Approach 1:
The voltage control unit provides dynamic voltage adjustment to the selection lines based on the bulk region voltage level. This dynamic control ensures that the voltage difference remains within safe limits even when the bulk region voltage is increased for efficient erasing, thereby preventing device deterioration and improving reliability while maintaining erasing efficiency
Solution Approach 2:
The voltage control unit proactively adjusts the selection line voltage before excessive voltage differences can cause damage. By anticipating the voltage changes in the bulk region during erasing operation and preemptively adjusting the selection line voltage, the system prevents harmful tunneling effects and device deterioration before they occur
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents device deterioration by maintaining voltage differences below tunneling thresholds, ensuring efficient erasing and programming operations while reducing leakage currents.
Implementation Method 1
A difference between the first and second voltages may be smaller than a voltage that can cause a tunneling effect in the first selection transistor
Data Source
AI summary
A flash memory device includes a bulk region, first through nth memory cell transistors arranged in a row on the bulk region, first through nth word lines respectively connected to gates of the first through nth memory cell transistors, a first dummy cell transistor connected to the first memory cell transistor, a first dummy word line connected to a gate of the first dummy cell transistor, a first selection transistor connected to the first dummy cell transistor, a first selection line connected to a gate of the first selection transistor, and a voltage control unit connected to the first selection line, the voltage control unit being adapted to output to the first selection line a voltage lower than a voltage applied to the bulk region, in an erasing mode for erasing the first through nth memory cell transistors.