Flash Memory Leakage Suppression via Soft Programming
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Solution Overview
Problem
Flash memory devices suffer from over-erasure issues, leading to leakage current and false read operations due to memory cells having threshold voltages below the minimum erased state, causing incorrect data retrieval.
Innovation Solution
A leakage-suppression process is implemented in block-based flash memory devices, where control logic detects and corrects over-erased memory cells by applying bias voltages to identify affected bit lines and performing a 'soft' programming operation to increase the threshold voltage, supported by erase status data to determine the need for the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a block of memory cells is erased, then all memory cells in the block are reset, but some memory cells become over-erased with threshold voltages below the minimum erased state, causing leakage current
Solution Approach 1:
The patent applies preliminary action by performing a leakage suppression process after the erase operation to detect and correct over-erased cells before they cause false reads. The control logic checks for over-erased cells and applies corrective programming operations to restore their threshold voltages to the proper erased state, preventing leakage current from affecting subsequent operations.
2Reliability
If over-erased memory cells are present, then leakage current flows on common bit lines, but this causes false readings during read operations of selected memory cells
Solution Approach 1:
The patent implements feedback by using the sense amplifier to detect current flow on bit lines during read operations. When over-erased cells cause leakage current that triggers a false read condition, the control logic receives this feedback and initiates a leakage suppression process to identify and correct the over-erased cells, thereby eliminating the source of false readings.
3Reliability
If a leakage suppression process is implemented to detect and correct over-erased cells, then leakage current is suppressed, but the process complexity increases
Solution Approach 1:
The patent applies universality by designing the leakage suppression process to handle multiple scenarios within a single framework. The control logic can detect over-erased cells, determine their locations, and apply corrective programming operations as needed. This multi-functional approach consolidates what would otherwise require separate circuits and operations into a unified process, managing complexity while achieving reliable leakage suppression.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses leakage current, preventing false read operations and ensuring accurate data retrieval by identifying and correcting over-erased cells, thereby improving the reliability of flash memory devices.
Implementation Method 1
Flash memory includes memory cells that store charge between the channel and gate of a field effect transistor. The charge stored affects the threshold voltage of the transistor.
Implementation Method 2
A memory cell can be programmed using various biasing techniques such as Fowler Nordheim (FN) tunneling, Channel Hot Electron (CHE), etc.
Implementation Method 3
A memory cell can be erased by applying a bias to induce hole tunneling into the charge storage layer, or to induce electron tunneling from the charge storage layer.
Implementation Method 4
The leakage-suppression process can include applying bias voltages sufficient to turn on over-erased memory cells, in order to identify corresponding bit lines that conduct leakage current.
Implementation Method 5
A 'soft' program operation is then performed to slightly increase the threshold voltage of the over-erased memory cells, thereby correcting the over erasure.
Data Source
AI summary
Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.