Flash Memory Floating Gate Liner Oxide Uniformity
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Solution Overview
Problem
The existing flash memory devices face issues with time-dependent dielectric breakdown (TDDB) and current leakage due to non-uniformity in the thickness of the floating gate silicon oxide layer, caused by the thermal oxidation process, leading to voids and reduced data retention performance.
Innovation Solution
The formation of liner oxide layers before shallow trench isolation structures addresses the non-uniformity by oxidizing the polysilicon layer, ensuring a consistent thickness and preventing the loading effect, which aids in forming a thicker tunnel oxide layer and a floating gate with a smaller bottom width, thereby improving the data retention and reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thermal oxidation process is used to form floating gate silicon oxide layer, then the layer can be formed, but non-uniformity in thickness occurs leading to TDDB and current leakage
Solution Approach 1:
A liner oxide layer is formed on the semiconductor substrate surface before forming the floating gate silicon oxide layer. This preliminary action creates a foundation that ensures uniform thickness and prevents the loading effect during subsequent oxidation, thereby eliminating TDDB and current leakage issues while improving data retention performance.
Solution Approach 2:
The liner oxide layer acts as an intermediary between the semiconductor substrate and the floating gate silicon oxide layer. This intermediate layer ensures uniform thickness distribution and prevents direct contact issues that cause non-uniformity, thereby resolving the contradiction between manufacturing precision and reliability.
2Object-affected harmful factors
If tunnel oxide layer thickness is increased to prevent leakage, then leakage reduction is achieved, but TDDB occurs due to non-uniform thickness
Solution Approach 1:
The liner oxide layer is formed in advance to provide a uniform foundation. This preliminary action allows the tunnel oxide layer to be formed with consistent thickness, preventing both current leakage and TDDB by ensuring uniform electrical properties throughout the layer.
Solution Approach 2:
By introducing the liner oxide layer, the oxidation parameters are effectively changed to produce a more uniform thickness distribution. This parameter change ensures that the tunnel oxide layer achieves the desired thickness for leakage prevention without the non-uniformity that causes TDDB.
3Manufacturing precision
If loading effect is prevented by oxidizing polysilicon layer, then uniform thickness is achieved, but additional process steps are required
Solution Approach 1:
The liner oxide layer formation is merged with the existing fabrication process flow, combining the oxidation of polysilicon layer with the tunnel oxide layer formation. This integration achieves uniform thickness while minimizing additional process complexity by utilizing established oxidation techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the uniformity and quality of the tunnel oxide layer, prevents TDDB and current leakage, and improves the data retention performance of the flash memory device by ensuring a consistent thickness and reducing the formation of voids in the floating gate.
Implementation Method 1
forming liner oxide layers by oxidizing the first polysilicon layer exposed by the first openings
Data Source
AI summary
The present application provides a flash memory device. The flash memory device includes a semiconductor substrate; and a plurality of tunnel oxide layers formed on a surface of the semiconductor substrate. The flash memory device also includes a floating gate having a first portion with a width smaller than a width of the tunnel oxide layer and a second portion with a width greater than the width of the first portion formed on the first portion formed on each of the floating silicon oxide layers. Further, the flash memory device includes a plurality of shallow trench isolation structures formed in the surface of the semiconductor substrate between adjacent floating gates and the tunnel oxide layers; and liner oxide layers formed on side surfaces of the first portion of the floating gates.