Byte-Alterable Flash Memory Array With Local Control Gates
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Solution Overview
Problem
Conventional flash memory arrays require entire rows or sectors to be erased or programmed, leading to increased operation time and reduced lifetime due to the sharing of common erase-gate and control-gate lines, which results in undesirable operations affecting unintended memory cells.
Innovation Solution
The implementation of a flash memory array structure with local control-gate lines disconnected from each other and connected to global control-gate lines, allowing for individual byte-level operations by using local and global control-gate lines, erase-gate lines, and bit-lines to control voltage application across memory cells, enabling selective erasure and programming of flash memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a common erase-gate line is shared by all memory cells in a row, then the structure is simple and easy to manufacture, but entire rows must be erased even when only part of the row needs erasing, causing increased operation time and reduced lifetime
Solution Approach 1:
The common erase-gate line is segmented into multiple row-specific erase-gate lines, each connected to a specific row of memory cells through row selection signals. This allows individual rows to be erased independently without affecting other rows, resolving the contradiction between structural simplicity and selective erasure capability.
Solution Approach 2:
The erase-gate line connectivity is made dynamic through row selection signals that activate only the specific erase-gate line corresponding to the target row. This dynamic activation enables selective erasure of individual rows while maintaining a relatively simple overall structure, balancing manufacturability with operational efficiency.
2Ease of manufacture
If a common control-gate line is used for all memory cells in a row, then the structure is simple, but entire rows must be programmed even when only individual cells need programming, reducing productivity and increasing operation time
Solution Approach 1:
The common control-gate line is divided into multiple row-specific control-gate lines, each可控 by row selection signals. This segmentation enables individual cells or groups of cells within a row to be programmed independently, significantly improving programming efficiency while maintaining structural simplicity through shared bit-line and source-line connections.
Solution Approach 2:
Different control-gate lines are assigned different local qualities through row selection signals, allowing specific rows to be activated for programming while keeping other rows inactive. This local activation enables selective programming of individual cells without requiring entire row programming, thereby improving productivity.
3Ease of operation
If entire rows are erased due to shared erase-gate lines, then the erase operation is simple to implement, but unintended memory cells are affected and must be written back, reducing lifetime
Solution Approach 1:
The erase-gate line is segmented into row-specific lines that can be selectively activated. This allows the erase operation to be simplified for the target row while preventing unintended erasure of other rows, thereby protecting memory cell lifetime from unnecessary program-erase cycles.
Solution Approach 2:
Row selection signals act as intermediaries between the control logic and the erase-gate lines. These intermediaries ensure that only the intended row receives the erase signal, preventing unintended erasure and subsequent rewrite operations that would reduce memory cell lifetime.
4Loss of time
If byte-level selective operations are enabled through local control-gate lines, then operation time is reduced and lifetime is increased, but the device complexity increases due to multiple disconnected local CG lines
Solution Approach 1:
The control-gate line structure is segmented into local and global components. Local control-gate lines are disconnected and connected to global control-gate lines through switching elements controlled by row selection signals. This segmentation enables byte-level selective operations while managing complexity through hierarchical organization.
Solution Approach 2:
The control-gate line structure implements a nested hierarchy where local control-gate lines are nested within global control-gate lines. The local lines are disconnected from each other but connected to global lines through row selection-controlled switches, enabling selective activation of specific rows while sharing common control infrastructure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces undesirable erase and program operations, thereby decreasing operation time and increasing the lifetime of flash memory cells by allowing for precise control over each byte, eliminating the need to write back data to unaffected cells.
Implementation Method 1
The floating gate is capable of holding charges and is separated from source and drain regions contained in a substrate by a layer of thin oxide
Implementation Method 2
The charges can be removed from the floating gate by tunneling the electrons to the source through the oxide layer during an erase operation
Implementation Method 3
A high voltage, for example, about 10V, is applied on control-gate 6, and thus the electrons are programmed into floating gate 4 under the influence of a high electrical field
Data Source
AI summary
An array of flash memory cells arranged in a plurality of rows and a plurality of columns includes a first row comprising a plurality of units. Each unit includes a plurality of flash memory cells, an erase-gate line connecting erase-gates of all flash memory cells in the first row, a source line connecting source nodes of all flash memory cells in the first row, a word line connecting word-line nodes of all flash memory cells in the first row, and a local control-gate (CG) line connecting control-gates of flash memory cells only in the unit, wherein each local CG line is disconnected from remaining local CG lines in the first row. The array further includes bit-lines each connecting bit-line nodes of flash memory cells in a same column.