Flash Memory Management Using Logical Page Size
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Solution Overview
Problem
Existing flash memory management systems perform poorly with random writes, especially in transaction-based computing systems and high-load applications, due to their assumption that pages can be written in any order, leading to slower random write performance compared to sequential writes.
Innovation Solution
Writing payload data to flash memory in the order it was received, allowing for improved random write performance by treating sequences of random data similarly to sequences of contiguous data, while preserving the time order of incoming data and eliminating position dependence within an erase block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If flash memory management systems assume pages can be written in any order, then device complexity is reduced, but random write performance deteriorates
Solution Approach 1:
The system performs preliminary sorting of incoming write requests before issuing them to the flash memory. The controller maintains a request queue and sorts requests based on target page addresses, ensuring that write operations are issued in an optimized sequence. This preliminary action resolves the contradiction by maintaining low device complexity while improving random write performance through intelligent request ordering.
2Reliability
If wear leveling distributes write cycles across the entire memory array, then reliability is improved, but write speed deteriorates
Solution Approach 1:
The memory array is segmented into multiple zones or regions, and the wear leveling algorithm operates at the zone level rather than requiring access to the entire array. This segmentation allows faster write operations within zones while still distributing wear across the full memory capacity over time, resolving the contradiction between reliability and write speed.
3Reliability
If logical page size is made smaller than physical page size, then data integrity is improved, but device complexity increases
Solution Approach 1:
The controller acts as an intermediary layer between the host system and the flash memory, maintaining a mapping table that translates logical page addresses to physical page addresses. This intermediary mechanism allows the use of smaller logical pages for better data integrity while managing the increased complexity through efficient address translation algorithms and data structures.
Data Source
AI summary
Disclosed are techniques for flash memory management, including tracking payload data via one or more data structures configured to define the size of logical pages in a flash memory. In various embodiments, the logical page size may be larger than, equal to, or smaller than a physical page size of a flash memory chip.