Flash Memory Mapping Structures for Error Correction
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Solution Overview
Problem
Flash memory devices suffer from high bit error rates due to inaccuracies during programming and charge loss over time and temperature, leading to reduced reliability and increased program-erase cycles, which are exacerbated by the need to erase entire blocks at once, resulting in insufficient error correction capabilities.
Innovation Solution
The implementation of a method that utilizes multiple mapping data structures of different granularities to manage flash memory, allowing for sequential writing of physical pages and random allocation of logical addresses, enabling efficient access and writing operations while optimizing error correction and reducing the number of program-erase cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple mapping data structures of different granularity are used to manage flash memory, then reliability and error correction capabilities are improved, but device complexity increases
Solution Approach 1:
The mapping system is divided into multiple data structures with different granularities (fine-grained mapping for precise address translation, coarse-grained mapping for block-level management). This segmentation allows each mapping structure to handle specific aspects of memory management, improving error correction capabilities while distributing complexity across multiple specialized components rather than one monolithic system
Solution Approach 2:
Multiple mapping data structures are nested hierarchically, with finer-grained mappings contained within or coordinated by coarser-grained mappings. This nested architecture enables layered error correction where each level provides protection for specific ranges of memory addresses, enhancing overall reliability while organizing complexity in a manageable hierarchical structure
2Productivity
If sequential writing of physical pages with random logical address allocation is implemented, then productivity is improved, but device complexity increases
Solution Approach 1:
Physical pages are prepared and organized in sequential order in advance, with mapping relationships pre-established between physical and logical addresses. This preliminary organization of physical storage resources allows write operations to proceed efficiently without real-time allocation decisions, improving productivity while the mapping structures handle the complexity of address translation
Solution Approach 2:
The mapping data structures maintain copies of address translation information at different granularities, allowing the system to quickly resolve logical to physical address mappings without complex real-time calculations. This copying approach enables efficient random logical address allocation while sequential physical writing, as the mapping copies provide rapid address resolution
3Duration of action of moving object
If the number of program-erase cycles is extended, then reliability is improved, but bit error rate increases
Solution Approach 1:
Multiple mapping data structures with different granularities are established in advance to provide layered error correction capabilities before errors occur. This preemptive error protection allows the system to correct bit errors that arise during extended program-erase cycles, enabling longer device lifetime while maintaining reliability through pre-configured correction mechanisms
Solution Approach 2:
The system dynamically adjusts error correction parameters based on the number of program-erase cycles and observed bit error rates. By changing correction thresholds and mapping granularity based on device aging and error patterns, the system can extend operational lifetime while adapting to increasing error rates over time
Data Source
AI summary
A method for accessing a flash memory, the method includes: receiving a read request that is associated with a logical address that is mapped to a physical address of a set of flash memory cells; accessing multiple mapping data structures of different granularity to obtain the physical address of the set of flash memory cells; wherein during at least one point in time at least one mapping data structure is stored in an erase block and wherein the erase block comprises multiple physical pages that are written in a sequential manner and are associated with logical page addresses that are assigned in a random manner; and reading a content of the set of flash memory cells.