Flash Memory Mapping Table Update via Buffer Parallelism

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Solution Overview

Problem

Conventional methods for updating mapping information in logical address-physical address mapping tables in flash memory modules result in low utility and performance of rewritable non-volatile memory modules due to the control circuit being in an idle state during the updating process.

Innovation Solution

A method that pre-loads the logical address-physical address mapping table into a buffer memory and updates it temporarily while the control circuit writes data into a physical programming unit, allowing the memory management circuit and control circuit to operate in parallel, thereby avoiding idle states and enhancing the memory module's performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the mapping table is updated using the conventional three-step method (loading, updating, storing), then the mapping information can be updated correctly, but the control circuit remains in an idle state during the updating process, reducing overall system utility

Engineering Contradiction:
Improvemapping information update correctnessVSAvoidsystem utility during mapping update
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The mapping table is pre-loaded into the buffer memory before the update operation begins. This allows the control circuit to continue processing write commands during the update process, eliminating the idle state while ensuring the mapping information is updated correctly through the preliminary preparation of data in buffer memory

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A buffer memory is introduced as an intermediary between the mapping table storage and the control circuit. The buffer memory temporarily holds the mapping table data, allowing the control circuit to access updated mapping information without stopping its operation, thus maintaining system utility while ensuring correct updates

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If the control circuit stops receiving commands to update the mapping table, then the mapping information can be updated accurately, but the rewritable non-volatile memory module cannot perform writing operations, reducing performance

Engineering Contradiction:
Improvemapping information update accuracyVSAvoidwriting operation performance
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The mapping table data is pre-loaded into the buffer memory before the update operation. This preliminary action allows the control circuit to continue processing write commands using the pre-loaded data, ensuring both accurate mapping updates and continuous writing operation performance

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The mapping table update process is segmented into separate operations: loading mapping data into buffer memory, updating the mapping information in the buffer, and storing the updated table back. This segmentation allows the control circuit to continue receiving and processing write commands during the update process, maintaining writing performance while ensuring update accuracy

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10402318B2Mapping table updating method, memory control circuit unit and memory storage device
Publication Date: 2019.09.03 HEFEI CORE STORAGE ELECTRONICS LTD
  • US10402318B2 patent drawing
  • US10402318B2 patent drawing
  • US10402318B2 patent drawing

AI summary

A mapping table updating method, a memory control circuit unit and a memory storage device. The method includes: receiving a first data corresponding to a first logical address from a host system; loading a first logical address-physical address mapping table according to the first logical address; sending a command sequence to a rewritable non-volatile memory module; in the process of writing the first data into a first physical programming unit according to the command sequence by a control circuit of the rewritable non-volatile memory module, updating the first logical address-physical address mapping table; and after writing the first data into the first physical programming unit by the control circuit, storing the updated first logical address-physical address table back to the rewritable non-volatile memory module.