Flash Memory Address Mapping Table Segmentation

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Solution Overview

Problem

Flash memory devices face challenges in maintaining address mapping tables during power shutdowns, leading to incomplete data transfer and prolonged boot times due to large data sizes and increased costs associated with capacitor-based solutions.

Innovation Solution

The address mapping table is divided into multiple units, with specific requirements determining when units are written to flash memory along with timestamps, allowing for efficient storage and rapid recovery upon power restoration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the entire address mapping table is written to flash memory before power shutdown, then data reliability is improved, but the write operation cannot be completed in time due to the large data size

Engineering Contradiction:
Improveaddress mapping table data reliabilityVSAvoidpower shutdown time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The address mapping table is divided into multiple units, each unit being a manageable chunk of data. Instead of treating the entire large mapping table as a single entity, the system segments it into smaller units that can be written to flash memory individually, allowing the write operation to complete before power shutdown while ensuring data reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary actions by writing address mapping table units to flash memory in advance, before power shutdown occurs. The controller continuously writes updated mapping table units to flash memory, so that when power shutdown happens, the most recent units are already persisted, eliminating the need to write the entire table at shutdown moment.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If capacitors are added to maintain power during shutdown, then data transfer completeness is improved, but manufacturing cost and device size increase

Engineering Contradiction:
Improvedata transfer completenessVSAvoidmanufacturing cost and device size
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent extracts the power maintenance function from the electrical domain (capacitors) and transfers it to the data domain (persistent storage in flash memory). Instead of using capacitors to maintain power, the system writes critical data units to flash memory which inherently retains data without power, thereby eliminating the need for additional capacitor components.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system uses flash memory blocks that can be easily erased and rewritten as a cheap, disposable resource for maintaining address mapping data. Rather than investing in expensive capacitor-based power maintenance, the system accepts that flash memory blocks can be rewritten periodically at low cost, using this inexpensive storage medium to ensure data persistence.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Reliability

If all address mapping table units are stored in flash memory, then data recovery is improved, but write bandwidth consumption and storage requirements increase

Engineering Contradiction:
Improveaddress mapping table recoveryVSAvoidstorage space and write bandwidth
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts only the essential address mapping table units from the complete mapping table and stores them in flash memory. Instead of persisting the entire mapping table, the system identifies and stores only those units that are critical for system recovery, thereby reducing storage space requirements and write bandwidth consumption while maintaining adequate recovery capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system performs partial action by writing only a subset of address mapping table units to flash memory rather than all units. The controller selectively writes mapping table units based on update frequency and importance, storing some units in flash memory while keeping others in volatile memory, thus achieving a balance between recovery reliability and resource consumption.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9329995B2Memory device and operating method thereof
Publication Date: 2016.05.03 VIA TECH INC
  • US9329995B2 patent drawing
  • US9329995B2 patent drawing
  • US9329995B2 patent drawing

AI summary

The invention provides a memory device. The memory device includes a flash memory, a memory, and a controller. The flash memory includes a plurality of blocks for data storage. The memory stores an address mapping table recording relationships between logical addresses and physical addresses of the blocks therein. The controller divides the address mapping table stored in the memory to a plurality of mapping table units, updates relationships between the logical addresses and the physical addresses stored in the mapping table units, determines whether data access performed to the flash memory fulfills the conditions of a specific requirement, and when the data access fulfills the conditions of the specific requirement, the controller selects a target mapping table unit from the mapping table units, and stores the target mapping table unit and a corresponding time stamp as a mapping table unit data to the flash memory.