Flash Memory Controller Midway Cache for Write Speed
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Solution Overview
Problem
The existing NAND flash memory technologies, particularly Multi Level Cell (MLC) NAND flash memory, face challenges in increasing access speed to improve the performance of flash memory storage systems, as they have slower programming speeds compared to Single Level Cell (SLC) NAND flash memory, despite offering higher capacity and lower costs.
Innovation Solution
A flash memory storage system and controller that categorize physical addresses into fast and slow categories, temporarily storing data in fast addresses and synchronously writing data to slow addresses in batches when a predetermined quantity is reached, utilizing a synchronization mechanism to enhance writing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC NAND flash memory is used to increase storage capacity and reduce cost, then storage capacity increases and cost decreases, but programming speed becomes slower
Solution Approach 1:
The patent segments physical addresses into fast physical addresses and slow physical addresses based on programming speed characteristics. This segmentation allows the system to differentiate between address types and apply appropriate writing strategies, enabling faster overall data writing by utilizing fast addresses for temporary storage and batch writing to slow addresses.
Solution Approach 2:
The patent introduces a buffer memory as an intermediary component between the host system and the flash memory. The buffer temporarily stores data before it is written to the flash memory, allowing the controller to manage writing operations more efficiently by batching writes to slow physical addresses while maintaining fast response to host requests.
2Reliability
If data is written directly to slow physical addresses in MLC NAND flash memory, then data is stored permanently, but writing time increases significantly
Solution Approach 1:
The patent performs preliminary actions by temporarily storing data in fast physical addresses or buffer memory before the final writing to slow physical addresses. This preliminary storage allows the system to acknowledge data receipt quickly while deferring the time-consuming write operation to slow addresses, effectively reducing perceived writing time while ensuring data is eventually stored permanently.
Solution Approach 2:
The patent implements periodic batch writing operations where data accumulated in the buffer or fast addresses is written to slow physical addresses in periodic batches. This periodic action pattern allows the system to maintain fast write acknowledgment while systematically transferring data to permanent storage locations, balancing speed and reliability requirements.
Data Source
AI summary
A flash memory storage system having a flash memory controller and a flash memory chip is provided. The flash memory controller configures a second physical unit of the flash memory chip as a midway cache physical unit corresponding to a first physical unit and temporarily stores first data corresponding to a first host write command and second data corresponding to a second host write command in the midway cache physical unit, wherein the first and second data corresponding to slow physical addresses of the first physical unit. Then, the flash memory controller synchronously copies the first and second data from the midway cache physical unit into the first physical unit, thereby shortening time for writing data into the flash memory chip.