Flash Memory Block Mode Switching for MLC Endurance
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Solution Overview
Problem
Multi-level cell (MLC) flash memory devices have limited endurance and fail quickly due to excessive program/erase cycles, leading to reduced storage capacity and accelerated deterioration, as defective blocks are removed from use, increasing the burden on remaining blocks and reducing system endurance.
Innovation Solution
A method and system that allow memory blocks in MLC flash memory circuits to operate in three modes: MLC, SLC, and defective modes, where blocks are initially in MLC mode, switching to SLC mode when error correction exceeds a threshold, and eventually to defective mode, thereby prolonging the life of the storage system by reducing the number of distribution states and extending the raw capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC flash memory is used to increase storage density, then storage capacity is improved, but the number of program/erase cycles is significantly reduced
Solution Approach 1:
The patent implements dynamic mode switching for memory blocks, allowing them to transition between MLC mode and SLC mode based on their condition. When error correction exceeds a threshold, blocks are switched from MLC to SLC mode, maintaining usability while reducing stress on remaining blocks. This dynamic adaptation resolves the contradiction by allowing high-density MLC operation when possible while providing a fallback to more durable SLC mode when reliability degrades.
Solution Approach 2:
The patent changes the operational parameters of memory blocks by switching between MLC and SLC modes. In MLC mode, two bits are stored per cell with tighter voltage thresholds, while in SLC mode, one bit per cell uses wider thresholds, improving reliability. This parameter change allows the system to optimize between storage density and endurance based on block condition and error rates.
2Reliability
If defective blocks are removed from use to maintain data integrity, then reliability is improved, but the burden on remaining blocks increases and system endurance is reduced
Solution Approach 1:
Instead of statically removing defective blocks, the patent implements dynamic mode switching where blocks transition from MLC to SLC mode when errors exceed thresholds. This keeps blocks in service longer, distributing wear more evenly across the memory array and extending system endurance while maintaining data integrity through error correction and mode adaptation.
Solution Approach 2:
The patent recovers potentially usable capacity by switching blocks to SLC mode rather than completely discarding them when errors occur. Blocks that would traditionally be marked defective and removed are instead recovered for continued use in a more conservative mode, extending their useful life and distributing the burden across more blocks.
3Reliability
If error correction threshold is set low to maintain data integrity, then reliability is improved, but storage capacity is reduced due to more blocks switching to SLC mode
Solution Approach 1:
The patent implements dynamic threshold monitoring and adaptive mode switching, where blocks transition from MLC to SLC mode based on real-time error correction performance. This allows the system to maintain high reliability by switching modes when needed while minimizing capacity loss by keeping blocks in MLC mode as long as error rates remain acceptable. The threshold is applied dynamically rather than statically, optimizing the balance between reliability and capacity.
Data Source
AI summary
Disclosed is an apparatus and method for operating a multi-level cell (MLC) flash memory circuit. Data is read from a memory block of a plurality of memory blocks in the MLC flash memory circuit, wherein each of the plurality of memory blocks can operate in one of at least three modes of operation comprising an MLC mode, a single-level cell (SLC) mode and a defective mode, and wherein the memory block is initially operating in the MLC mode. Error correction is performed on the read data to correct read errors in the read data. A determination is made if a number of bits corrected by the error correction exceeds a predetermined threshold value. If the number of bits corrected by the error correction exceeds the predetermined threshold value, the operating mode of the memory block is switched from the MLC mode to the SLC mode.