Multi-Level Flash Memory Cell Endurance Extension via Mode Transition
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Solution Overview
Problem
Multi-level flash memory devices have a shorter life cycle and lower reliability due to the diminishing ability to distinguish between closely spaced threshold states as the device ages, leading to a transition from multi-level to reduced capacity operating mode.
Innovation Solution
A technique that involves setting all bits of a portion of the memory to a specific value to transition from multi-level to reduced capacity mode, maintaining the largest spacing between threshold levels, allowing the device to store data more reliably by designating threshold windows and programming only critical data in single-level cell mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cells store multiple bits per cell by applying multiple programming pulses, then storage capacity increases, but reliability and endurance deteriorate due to shorter life cycle and difficulty in distinguishing closely spaced threshold levels
Solution Approach 1:
The memory device dynamically transitions between multi-level cell mode and single-level cell mode based on detected conditions. When a condition indicating deteriorated state discrimination is detected, the device switches from storing multiple bits per cell to storing one bit per cell, thereby adapting the storage capacity to maintain reliability
Solution Approach 2:
The invention changes the operational parameters of the memory cells by switching between different programming modes. In multi-level mode, multiple threshold levels are programmed to store multiple bits. When reliability deteriorates, the system changes parameters to single-level mode with larger threshold spacing, improving state distinguishability
2Quantity of substance
If multi-level cells use closely spaced threshold levels to store multiple bits, then storage density increases, but the ability to distinguish between states diminishes as the device ages
Solution Approach 1:
The system dynamically adjusts the threshold level spacing by switching between operational modes. Initially, closely spaced thresholds enable multi-bit storage. As the device ages and state distinction becomes difficult, the system transitions to widely spaced thresholds with single-bit storage, maintaining measurement precision
Solution Approach 2:
The invention segments the operational history of the memory device into different phases: an initial phase using multi-level cells with closely spaced thresholds for high density, and a later phase using single-level cells with widely spaced thresholds for reliable state distinction. The transition between segments is triggered by detecting deterioration in state discrimination
3Reliability
If the device transitions from multi-level to reduced capacity mode to maintain reliability, then state distinction improves, but storage capacity decreases
Solution Approach 1:
The memory device dynamically transitions between operational modes based on detected conditions. When state distinction becomes difficult, the device automatically reduces capacity by switching to single-level cell mode, accepting lower storage capacity in exchange for maintained reliability
Solution Approach 2:
The system discards the high-capacity multi-level storage mode when reliability deteriorates, transitioning to a lower-capacity single-level mode. This discarding of capacity enables recovery of reliable operation, and the transition can be reversed if conditions improve
Data Source
AI summary
A novel technique to improve and extend endurance and reliability of a memory device utilizing multi-level cells is disclosed. As a memory device ages, it's reliability deteriorates. Prior to the memory device becoming completely unreliable, the memory device transitions from a multi-level cell operating mode to a reduced capacity operating mode. When operating in the multi-level cell mode, the memory system stores multiple bits per cell. The memory system stores fewer bits per cell when operating in the reduced capacity. The transition between modes is achieved by setting all bits of a particular memory page to a specific value, for example, either a logic “1” or a logic “0.”