Flash Memory Multi-Bit Read Error Correction
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Solution Overview
Problem
Current flash memory devices face challenges in maintaining data accuracy due to voltage coupling and cell-to-cell coupling, which can lead to errors during data read and write operations.
Innovation Solution
The implementation of multilevel memory cells that utilize additional data states beyond traditional binary storage to store error information, where extra states are used to provide error detection and correction, rather than increasing storage capacity, by designating specific states as error bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage coupling and cell-to-cell coupling are present in flash memory, then memory operation can be performed, but data accuracy deteriorates due to errors during read and write operations
Solution Approach 1:
The patent implements error detection and correction mechanisms that provide feedback about the quality of stored data. By monitoring for errors caused by voltage coupling and cell-to-cell coupling, the system can correct data without requiring physical changes to the memory structure, thus improving data accuracy while maintaining the existing harmful coupling effects.
Solution Approach 2:
The patent changes the parameter of data representation by using multiple voltage levels (multi-level cell) to encode not only data but also error information. This allows the system to distinguish between valid data states and error states, enabling correction of errors caused by voltage coupling and cell-to-cell coupling through parameter-based identification rather than physical isolation.
2Reliability
If additional data states are used to store error information, then data integrity is improved through error detection and correction, but storage capacity is not increased
Solution Approach 1:
The patent makes the memory cells multi-functional by using the same physical storage structure to serve dual purposes: storing data and storing error information. The additional data states are not used to increase capacity but to provide error detection and correction capabilities, allowing one structure to perform multiple functions simultaneously.
Solution Approach 2:
The patent introduces error information as an intermediary element within the data storage structure. By incorporating error states as part of the multi-level cell architecture, the system can detect and correct errors without adding separate error correction memory, thus improving data integrity without proportionally increasing storage capacity.
3Quantity of substance
If multilevel memory cells are used to store multiple bits, then storage capacity increases, but data accuracy decreases due to increased likelihood of multiple state changes
Solution Approach 1:
The patent uses feedback mechanisms to monitor the stability of multi-level cell states. By incorporating error detection that specifically monitors for multiple state changes, the system can identify when data integrity is compromised and correct the errors, thereby maintaining high data accuracy even while using multilevel cells for increased storage capacity.
Solution Approach 2:
The patent performs preliminary error detection and correction actions before data errors can propagate or cause system failures. By pre-identifying error states through the multi-level cell error detection mechanism, the system can correct data accuracy issues proactively, allowing the use of high-capacity multilevel cells without sacrificing reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data integrity by allowing for the identification and correction of errors, providing a confidence factor in the accuracy of stored data and reducing the likelihood of multiple state changes, thus improving overall memory device performance.
Implementation Method 1
Because the FG is isolated by its insulating oxide layer, any electrons placed on it get trapped there and thus store the information.
Implementation Method 2
When electrons are trapped on the FG, they modify (partially cancel out) an electric field coming from the CG, which modifies the threshold voltage (Vt) of the cell.
Implementation Method 3
when the cell is 'read' by placing a specific voltage on the CG, electrical current will either flow or not flow between the cell's source and drain connections, depending on the Vt of the cell.
Data Source
AI summary
A memory device is described that comprises determining which read data state of more than 2X read data states a memory cell is in after the memory cell has been programmed to one of 2X program data states, wherein the determined read data state corresponds to X digits of read data and at least one digit of error data, and wherein X is a positive integer.