Flash Memory Erasing with Multi-Level Wordline Bias
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Solution Overview
Problem
Flash memory devices experience a wide distribution of threshold voltages after erasing due to variations in erasure-coupling ratios across memory cells, leading to differences in erasing speeds and inefficiencies.
Innovation Solution
Applying different electric fields between a bulk region and multiple wordlines with varying voltages to adjust the erasing speeds of memory cells, with higher voltages applied to wordlines connected to fast-erasing cells and lower voltages to slow-erasing cells, and using a voltage generator to select these voltages based on data about erasing speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a single erasing voltage is applied to the bulk region for all memory cells, then the erasing operation is simple to implement, but the threshold voltage distribution becomes wide due to variations in erasure-coupling ratios
Solution Approach 1:
The patent applies different wordline voltages to different wordlines based on their specific erasure characteristics. Memory cells are divided into groups according to their erasure-coupling ratios, and each group receives a tailored wordline voltage to achieve uniform threshold voltage distribution across all cells.
Solution Approach 2:
The patent changes the wordline voltage parameter to compensate for variations in erasure-coupling ratios. By adjusting the wordline voltage levels dynamically based on measured erasure characteristics, the system optimizes the erasing operation to achieve narrow threshold voltage distribution.
2Manufacturing precision
If different wordline voltages are applied to compensate for erasure speed variations, then the threshold voltage distribution is narrowed, but the device complexity increases due to multiple voltage levels
Solution Approach 1:
The patent segments the memory cell array into multiple groups based on their erasure characteristics, with each group associated with a specific wordline voltage level. This segmentation allows targeted control of erasure speeds while maintaining manageable system complexity through organized voltage generation.
Solution Approach 2:
The patent implements dynamic voltage selection where the wordline voltage is adjusted based on the specific memory block being erased and its measured erasure characteristics. The voltage generator dynamically selects from multiple predefined voltage levels to optimize erasure performance for different cell groups.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach narrows the post-erasing threshold-voltage distribution profile, ensuring more uniform erasing speeds and improving the stability of subsequent programming operations by addressing the inefficiencies in existing erasing methods.
Implementation Method 1
there is tunnel capacitance C2 through the tunnel oxide film between the floating gate 20 and the P-well 40 to facilitate Fowler-Nordheim tunneling (F-N tunneling). Under this bias condition, electrons move from the floating gate 20 toward the P-well 40 through the tunnel oxide film by way of the F-N tunneling effect induced by a DC voltage distributed at the tunnel capacitance C2.
Data Source
AI summary
Methods of erasing data in a flash memory device are provided in which a plurality of wordline bias voltages are generated that include wordline bias voltages having at least two different levels, erasing data by applying the different wordline bias voltages to respective ones of a plurality of wordlines while applying an erasing voltage to a bulk region of memory cells, and verifying the erased states of the memory cells. Pursuant to these methods, the spread of the threshold-voltage distribution profile that may result from deviations of erasure-coupling ratios between memory cells may be reduced.