Flash Memory Controller Multi-Plane Command Sequencing

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Solution Overview

Problem

Conventional flash memory devices require complex command sequences and longer waiting times to access multiple planes, leading to inefficiencies in data transmission and processing operations.

Innovation Solution

A flash memory device and controller system with an I/O control circuit, command register, data register, and control circuit that perform a data toggle operation to sequentially transmit data units from multiple planes using a single command sequence, simplifying the communication interface and reducing waiting times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple command sequences are used to access multiple planes, then data transmission completeness is improved, but command sequence complexity increases

Engineering Contradiction:

Improvedata transmission completenessVSAvoidcommand sequence complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple command sequences into a single unified command sequence that can access multiple planes. The control circuit receives one command sequence containing addresses for multiple planes and sequentially transmits data from each plane without requiring separate command sequences, thereby reducing command complexity while maintaining complete data transmission.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The control circuit is designed with multi-functionality to handle commands for multiple planes within a single command sequence. It can identify and process addresses corresponding to different planes (first plane, second plane, third plane) and retrieve data from each plane using the same command structure, making the system universal across multiple storage locations.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If multiple command sequences are used to access multiple planes, then data transmission completeness is improved, but waiting time increases

Engineering Contradiction:

Improvedata transmission completenessVSAvoidwaiting time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The control circuit implements continuous data transmission by sequentially retrieving and transmitting data from multiple planes without interrupting the command flow. After receiving a single command sequence, it continuously accesses the first plane, then the second plane, then the third plane, and transmits all data in an unbroken sequence, eliminating idle waiting time between plane accesses.

Inventive Principle:

Principle #20Continuity of useful action

Solution Approach 2:

The control circuit performs preliminary identification of all plane addresses within the single command sequence before execution. It parses the command sequence to identify addresses for the first plane, second plane, and third plane in advance, preparing the retrieval sequence beforehand to minimize waiting time during actual data transmission.

Inventive Principle:

Principle #10Preliminary action

3Device complexity

If a single command sequence is used to access multiple planes, then command sequence complexity is reduced, but data access capability may be compromised

Engineering Contradiction:

Improvecommand sequence complexityVSAvoiddata access capability

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The control circuit segments the single command sequence into distinct address components corresponding to different planes. It identifies and separates addresses for the first plane, second plane, and third plane within the unified command structure, allowing independent access to each plane's data while maintaining overall command simplicity.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS11861212B2Flash memory device, controller, and method capable of performing access operation upon data unit(s) of multiple planes of flash memory device in response one simplified command sequence

Publication Date: 2024.01.02 SILICON MOTION INC

AI summary

A flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller into a simplified command sequence so as to reduce the waiting time period of the command transmission and improve the performance of flash memory.