Flash Memory Controller Multi-Plane Command Simplification

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Solution Overview

Problem

Conventional flash memory devices require complex command sequences and longer waiting times to access multiple planes, complicating operations such as data read, write, and erase operations.

Innovation Solution

A flash memory device and controller system with an I/O control circuit, command register, and control circuit that perform a data toggle operation to sequentially transmit data units from multiple planes using a single command sequence, reducing the complexity and waiting time of command transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple command sequences are used to access multiple planes, then data access completeness is improved, but command complexity and waiting time increase

Engineering Contradiction:

Improvedata access completenessVSAvoidcommand sequence complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple plane access operations into a single command sequence. The control circuit receives one command that triggers sequential access to first data units from a first plane and second data units from a second plane, merging what would traditionally require separate command sequences into a unified operation.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent implements continuous data transmission by buffering first data units and second data units in a data register, then sequentially transmitting them without interruption. This eliminates the waiting periods between separate command sequences while maintaining complete data access across multiple planes.

Inventive Principle:

Principle #20Continuity of useful action

2Reliability

If multiple command sequences are used to access multiple planes, then all data units are retrieved, but transmission waiting time increases

Engineering Contradiction:

Improvedata retrieval completenessVSAvoidcommand transmission waiting time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary buffering of data units from multiple planes in the data register before transmission. This allows the control circuit to prepare all necessary data in advance, so that sequential transmission can occur without waiting for separate command execution cycles, thereby reducing overall waiting time while ensuring complete data retrieval.

Inventive Principle:

Principle #10Preliminary action

3Measurement precision

If separate command sequences are used for each plane, then plane-specific control is precise, but operation efficiency decreases

Engineering Contradiction:

Improveplane-specific control precisionVSAvoidoperation efficiency

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The patent creates a universal command structure that can access multiple planes through a single command sequence. The control circuit interprets the command to sequentially access first data units from a first plane and second data units from a second plane, making the command system multi-functional while maintaining precise plane-specific control through the sequential access mechanism.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12164805B2Flash memory device, controller, and method capable of performing access operation upon data unit(s) of multiple planes of flash memory device in response one simplified command sequence

Publication Date: 2024.12.10 SILICON MOTION INC

AI summary

A flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller into a simplified command sequence so as to reduce the waiting time period of the command transmission and improve the performance of flash memory.