Flash Memory Read Reliability via Multi-Voltage Soft Data Decoding
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Solution Overview
Problem
Flash memory devices face challenges in efficiently detecting and correcting read errors in multi-bit data storage due to overlapping threshold voltage distributions, which lead to increased error bits and reduced reliability as the number of bits programmed in each memory cell increases.
Innovation Solution
The implementation of control circuitry in flash memory devices that applies multiple read voltages, including a read reference voltage and variable voltages, to decode hard and soft data values from N-bit memory cells, enabling the generation of reliability data for error correction without additional circuitry, thereby enhancing error correction efficiency and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit data is programmed in each memory cell to increase storage capacity, then data storage capacity increases, but read reliability decreases due to overlapping threshold voltage distributions
Solution Approach 1:
The patent segments the read operation into multiple stages, applying different read voltages (first read voltage, second read voltage, third read voltage) to sequentially determine different bits of multi-bit data. This segmentation allows the system to handle the complexity of overlapping threshold voltage distributions by breaking down the read process into manageable steps, thereby maintaining high storage capacity while improving read reliability
Solution Approach 2:
The patent applies preliminary actions by performing threshold voltage distribution analysis and selecting appropriate read voltages before the actual read operation. The control circuitry determines the threshold voltage distribution characteristics in advance and selects read voltages that are optimally positioned to distinguish between adjacent threshold voltage distributions, thereby preventing read errors before they occur
2Device complexity
If the number of bits programmed in each memory cell increases to improve integration, then high integration is achieved, but error bits increase due to decreased distance between threshold voltage distributions
Solution Approach 1:
The patent employs dynamic read voltage selection based on the actual threshold voltage distribution characteristics of the memory cells. The control circuitry adjusts the read voltages dynamically according to the programmed data patterns and observed threshold voltage distributions, allowing the system to maintain high integration with multi-bit cells while adapting to varying error conditions to minimize error bits
Solution Approach 2:
The patent implements feedback mechanisms where the control circuitry monitors the read results and threshold voltage distributions, then adjusts subsequent read operations accordingly. When error bits are detected or threshold voltage distributions show signs of overlap, the system modifies the read voltage selection and re-performs reads, creating a feedback loop that continuously optimizes read reliability while maintaining high integration
3Reliability
If additional circuitry is added to detect and correct read errors, then error correction capability improves, but chip size increases
Solution Approach 1:
The patent makes the control circuitry universal by designing it to perform multiple functions: normal read operations, threshold voltage distribution analysis, read voltage selection, and error detection/correction. This multi-functionality allows the same circuitry to handle both standard operations and error correction without requiring separate dedicated circuits, thereby improving error correction capability while avoiding chip size increase
Solution Approach 2:
The patent enables the memory system to self-correct errors through intelligent control algorithms that analyze threshold voltage distributions and automatically adjust read voltages to retrieve accurate data. The control circuitry serves itself by using the same hardware resources to both detect errors and correct them through iterative reading and analysis, eliminating the need for separate error correction circuitry and maintaining compact chip size
Data Source
AI summary
Integrated circuit memory devices include an array of nonvolatile N-bit memory cells, where N is an integer greater than one. Control circuitry is also provided to reliably read data from the N-bit memory cells. This control circuitry, which is electrically coupled to the array, is configured to determine, among other things, a value of at least one bit of data stored in a selected N-bit memory cell in the array. This is done by decoding at least one hard data value and a plurality of soft data values (e.g., 6 data values) read from the selected N-bit memory cell using a corresponding plurality of unequal read voltages applied to the selected N-bit memory cell during a read operation.