Flash Memory Read Control Using Multi-Voltage Cell Sensing
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Solution Overview
Problem
Existing flash memory devices, particularly those with quadruple level cell (QLC) technology, face inefficiencies in access control due to high bit error rates and instability, where traditional sensing schemes fail to effectively manage data reading, especially in high-density storage arrangements.
Innovation Solution
A method involving a flash memory module and controller that uses multiple read voltages to read each memory cell, transmitting multi-bit information to decode operations efficiently, employing sense amplifiers and a control logic circuit to de-randomize and decode data within the flash memory module, thereby improving read efficiency and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional sensing schemes are used for reading data from QLC flash memories, then the existing read mechanism can be maintained, but the bit error rate increases and read efficiency decreases due to high-density storage arrangements
Solution Approach 1:
The patent segments the read operation into multiple phases by applying different read voltages to sense amplifier pairs sequentially. Each phase reads a portion of the multi-bit information stored in memory cells, allowing the system to handle high-density QLC storage by breaking down the complex read operation into manageable segments that can be processed reliably
Solution Approach 2:
The patent introduces a new dimension to the read mechanism by utilizing multiple sense amplifier pairs with different read voltages simultaneously or sequentially. This dimensional expansion allows the system to extract multi-bit information from each memory cell more effectively, improving both reliability and efficiency in QLC flash memories
2Productivity
If multiple read voltages are applied to read each memory cell, then multi-bit information can be obtained efficiently, but the complexity of the read mechanism increases
Solution Approach 1:
The patent merges multiple sense amplifier pairs into a coordinated system where each pair handles specific voltage levels. By combining their outputs through logical operations, the system efficiently retrieves multi-bit information without requiring separate complex read paths for each voltage level, thus improving productivity while managing complexity
Solution Approach 2:
The sense amplifier pairs are designed to be multi-functional, capable of operating with different read voltages and handling multiple bit readings. This universality allows the same hardware structure to perform multiple functions across different read phases, reducing overall system complexity while maintaining high read efficiency
Data Source
AI summary
The present invention provides an electronic device, wherein the electronic device includes a flash memory module and a flash memory controller. The flash memory module includes at least one flash memory chip, each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages, and the flash memory controller is configured to access the flash memory module. In the operations of the electronic device, when the flash memory controller sends a read command to the flash memory module to ask for data on at least one page, the flash memory module uses a plurality of read voltages to read each memory cell of the at least one page to obtain multi-bit information of each memory cell, and the flash memory module transmits the multi-bit information of each memory cell of the at least one page to the flash memory controller.