Flash Memory Network with Redundant Flashbus Channels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory systems face bottlenecks in data distribution and reliability due to limitations in interconnects between multiple chip controllers and flash memory modules, particularly in high-performance systems, where failure of one component can disrupt overall system operation.
Innovation Solution
A network of memory systems is designed with multiple system controllers and flash memory modules interconnected via a high-speed flashbus, providing redundant paths to ensure continuous operation even if one controller or module fails, utilizing flash-specific DMA controllers and arbiters to manage data transactions and bus access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple chip controllers and flash memory modules are interconnected to increase memory capacity and performance, then data access throughput is improved, but data distribution bottlenecks occur due to interconnect limitations
Solution Approach 1:
The system divides the memory interconnect into multiple independent flashbus channels, each capable of autonomous data transmission. This segmentation allows parallel data distribution across multiple paths, eliminating the single-bus bottleneck while maintaining manageable complexity through modular channel design.
Solution Approach 2:
The patent transitions from a single-dimension serial interconnect to a multi-dimensional parallel interconnect structure. Multiple flashbus channels operate simultaneously in different data paths, creating a two-dimensional data distribution network that increases throughput without proportionally increasing interconnect complexity.
2Reliability
If redundant controllers are implemented to improve system reliability, then fault tolerance is enhanced, but system complexity increases
Solution Approach 1:
Multiple controllers are merged into a unified system where each controller manages specific flashbus channels. The controllers share common resources and coordinate through standardized protocols, achieving fault tolerance while controlling complexity through resource sharing and modular architecture.
Solution Approach 2:
The controller architecture implements dynamic failover capabilities where control functions can be dynamically transferred between controllers based on operational status. This dynamic allocation allows the system to maintain reliability without requiring complex static redundancy configurations.
3Quantity of substance
If flash memory capacity is increased to meet high-end storage market needs, then storage capability is improved, but data distribution bottlenecks worsen
Solution Approach 1:
Large capacity flash memory systems are segmented into multiple flashbus channels, each handling a portion of the total data traffic. This segmentation distributes the data transfer load across multiple parallel paths, maintaining efficient data distribution even as total memory capacity increases.
Solution Approach 2:
The patent implements multiple copies of the flashbus interconnect structure, creating parallel data paths that can simultaneously transmit data to different memory modules. This copying approach enables scalable capacity expansion without creating single-point data distribution bottlenecks.
Data Source
AI summary
A large network of memory system is described comprising a plurality of system controllers and flash memory modules, in accordance with an embodiment of the invention. An apparatus is also described comprising a plurality of flash memory modules interconnected with other flash memory modules and to at least one system controller via a point-to-point communication bus topology, in accordance with another embodiment of the invention.