Flash Memory NFI Margin Testing for Reliable High-Speed I/O
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Increasing the bus rate of a nonvolatile flash interface (NFI) in flash memory chips leads to reduced bus link reliability and data loss due to single-bit errors, which are exacerbated by the increasing number of channels, adversely affecting read and write performance.
Innovation Solution
Optimize selected channels in the NFI bus during normal operation without disk disconnection by determining optimization parameters such as read and write reference voltages and timing margins, adjusting the DQS signal delay lines to maximize timing margins, and performing margin tests to identify channels that need optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the bus rate of the NFI interface is increased to improve I/O rate, then the read/write performance is improved, but the bus link reliability is reduced and data loss occurs due to single-bit errors
Solution Approach 1:
The patent adjusts timing parameters (setup time, hold time, data width) and voltage parameters dynamically based on the bus rate to optimize the balance between I/O performance and transmission reliability. Different channels are assigned different optimization parameters according to their actual transmission quality, resolving the contradiction between high speed and high reliability through parameter adaptation.
2Productivity
If the quantity of NFI bus channels is increased to improve I/O rate, then the read/write performance is improved, but the probability of single-bit errors increases accordingly
Solution Approach 1:
The patent performs margin tests on each channel individually and determines optimization parameters specific to each channel's transmission quality. Channels with better transmission quality can operate at higher speeds while channels with poorer quality are optimized for reliability, allowing the system to maximize overall I/O performance while managing error probabilities through localized optimization.
3Reliability
If data resending is implemented to correct single-bit errors, then the reliability is improved, but the read and write performance is degraded
Solution Approach 1:
The patent performs margin tests and determines optimization parameters in advance before actual data transmission. By pre-configuring the optimal data width, setup time, and hold time for each channel based on their transmission characteristics, the system avoids the need for data resending during normal operation, thus maintaining high performance while ensuring reliability.
Data Source
AI summary
Embodiments of the present disclosure provide a method for optimizing a flash memory chip and a related apparatus. The method comprises, after completing write training of a nonvolatile flash interface (NFI) and establishing a data strobe signal (DQS) trigger point that triggers a memory to identify an electrical level state of a write data signal (DQ) corresponding to the DQS trigger point, determining whether a trigger condition for monitoring the NFI is met, wherein the trigger condition is related to working environmental data of the NFI; upon determining that the trigger condition for monitoring the NFI is met, writing test data to the memory and performing a margin test on the NFI to determine whether the NFI passes a margin test; and upon determining that the NFI does not pass the margin test, initiating interface retraining of the NFI. In this way, the NFI bus channels can be optimized without disk disconnection.