Flash Memory NFI Bus Tuning for Lower Transmission Errors
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Solution Overview
Problem
Increasing the bus rate of a nonvolatile flash interface (NFI) in flash memory chips leads to reduced bus link reliability and data loss due to single-bit errors, which are exacerbated by the increasing number of NFI bus channels, adversely affecting read and write performance.
Innovation Solution
Optimize selected channels in the NFI bus by determining optimization parameters through margin testing and training data, adjusting read and write reference voltages and DQS timing to align timing margins and reduce error probability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the bus rate of the NFI interface is increased to improve I/O rate, then read/write performance is improved, but bus link reliability is reduced and data loss occurs
Solution Approach 1:
The patent adjusts timing parameters (setup time, hold time, data width) and voltage parameters (reference voltage levels) of the NFI interface to optimize the balance between transmission speed and reliability. By dynamically changing these parameters, the system achieves high I/O rates while maintaining sufficient timing margins to prevent data loss.
2Productivity
If the number of NFI bus channels is increased to improve data throughput, then I/O rate is improved, but the probability of single-bit errors increases
Solution Approach 1:
The patent applies different timing and voltage optimization parameters to different channels of the NFI bus based on their individual characteristics. Each channel undergoes separate margin testing and receives customized parameter settings, ensuring that each channel operates at optimal reliability levels while maintaining high overall throughput.
3Reliability
If data resending is implemented to correct single-bit errors, then data accuracy is improved, but read and write performance is degraded
Solution Approach 1:
The patent performs margin testing and parameter optimization in advance during the initialization phase, before actual data transmission begins. By pre-configuring optimal timing and voltage parameters for each channel, the system prevents errors from occurring in the first place, eliminating the need for error correction through data resending and thus maintaining high transmission performance.
Data Source
AI summary
Embodiments of this application provide a method for optimizing a flash memory chip and a related apparatus. According to the method, some channels in a nonvolatile flash interface NFI bus of the flash memory chip may be suspended in a service running process of the flash memory chip; a to-be-optimized channel that needs to be optimized is determined from the suspended channels; an optimization parameter of each to-be-optimized channel is determined based on training data of each to-be-optimized channel; and each to-be-optimized channel is optimized based on the optimization parameter of each to-be-optimized channel. In the foregoing technical solution, the some channels in the NFI bus can be optimized in the normal running process of the flash memory chip. In other words, the other channels can maintain a normal working state. In this way, the NFI bus channel can be optimized without disk disconnection.