Flash Memory Functional State Configurable Opcode Routing
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Solution Overview
Problem
Integrated circuits face challenges in running from conventional Flash memory when it is busy with operations like erasing or re-programming, requiring additional physical memory blocks or stalling the processor, which increases die size and cost.
Innovation Solution
Incorporating a multiplexer and logic circuitry in the memory system that supplies a benign opcode to the processor when the Flash memory is busy, allowing uninterrupted opcode fetch and execution without changing program flow or suspending processor operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a second physical block of program memory is provided to enable mission mode reprogramming, then reprogramming capability is improved, but die area and cost increase
Solution Approach 1:
The single Flash memory block is made multi-functional by implementing different operational modes (read mode and reprogramming mode) within the same physical structure. The memory block can serve both as program memory during normal operation and as reprogramming target during mission mode updates, eliminating the need for separate memory blocks.
Solution Approach 2:
A boot loader mechanism acts as an intermediary layer between the processor and the Flash memory. The boot loader resides in a protected region of the same Flash block and coordinates the reprogramming process, enabling the single memory block to handle both boot operations and reprogramming tasks without requiring additional memory hardware.
2Reliability
If the processor is stalled while Flash is busy with erasing or re-programming, then data integrity is improved, but productivity decreases
Solution Approach 1:
The Flash memory block is segmented into different operational regions and states. The memory is divided into protected regions (containing boot loader and critical code) and reprogrammable regions. During reprogramming, the processor can continue executing from protected regions while the reprogrammable regions are updated, avoiding complete processor stalling.
Solution Approach 2:
The boot loader is pre-loaded into a protected region of the Flash memory before reprogramming operations begin. This preliminary action ensures that the processor has a valid code path to execute during the reprogramming process, maintaining productivity while ensuring data integrity through the protected boot region.
3Adaptability or versatility
If conventional Flash memory operations are performed, then memory functionality is improved, but processor operation is interrupted when memory is busy
Solution Approach 1:
The memory system implements dynamic operational states with automatic mode switching. The Flash memory block dynamically transitions between read mode and reprogramming mode based on the operational phase. During normal operation, the memory functions as read-only program memory; during reprogramming, it dynamically switches to allow write operations while maintaining processor execution through the boot loader mechanism.
Data Source
AI summary
An integrated circuit comprises a processor configured for fetching and executing opcodes, a system bus, and a memory coupled to the processor via the system bus. The memory includes logic circuitry for detecting functional states of the memory, wherein the memory (a) supplies one or more programmed opcodes in response to detection of first functional states of the memory, and (b) supplies a hard coded opcode in response to detection of second functional states of the memory. The second functional states of the memory can include one or more of erase, write, self-test, and check-sum. The first functional states of the memory can include a functional state other than a second functional state.