Flash Memory Output Buffer SDR DDR Mode Switching

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Solution Overview

Problem

Flash memory devices face limitations in reducing the number of pins while maintaining fast data transmission capabilities, which is essential for efficient operation in systems like SSDs and memory modules.

Innovation Solution

The implementation of a unified data fetch scheme using a single data fetch signal (/RWE) and control logic circuitry to discriminate data input/output cycles, allowing for reduced pin count and enabling edge alignment and double data rate modes for synchronized data transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a unified data fetch scheme using a single data fetch signal is implemented, then the number of pins is reduced, but data transmission speed capability is limited

Engineering Contradiction:

Improvenumber of pinsVSAvoiddata transmission speed

Core Design Contradiction:

Device complexityVSSpeed

Solution Approach 1:

The patent implements dynamic operation modes where the same single data fetch signal can operate in different modes (SDR mode and DDR mode) depending on the operational requirements. The output buffer circuit can dynamically switch between serial access mode and double data rate mode, allowing the system to adapt its data transmission characteristics without changing the physical pin configuration.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameters of the data fetch signal by generating a second data fetch signal with different timing characteristics. By delaying the first data fetch signal and creating edge-aligned signals, the system can achieve faster effective data transmission rates (up to 200 MHz) while using the same physical pin, thus resolving the contradiction between pin reduction and speed maintenance.

Inventive Principle:

Principle #35Parameter changes

2Speed

If edge alignment mode is implemented for synchronized data transfer, then data transmission frequency is increased, but control logic complexity increases

Engineering Contradiction:

Improvedata transmission frequencyVSAvoidcontrol logic complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The signal generator performs preliminary action by pre-calculating and pre-positioning the second data fetch signal with the appropriate delay and edge alignment. This preliminary signal preparation allows the output buffer circuit to receive properly timed signals without requiring complex real-time control logic, thus achieving high-frequency data transfer while limiting the increase in control logic complexity.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS9715936B2Flash memory device for outputing data in synch with a first signal in an SDR mode and a DDR mode and a flash memory system including the same

Publication Date: 2017.07.25 SAMSUNG ELECTRONICS CO LTD

AI summary

A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.