Flash Memory Page Buffer Read Performance Noise Control
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Solution Overview
Problem
Flash memory devices experience data errors due to noise associated with power voltage fluctuations during cache read operations, which degrade channel conditions and lead to data errors.
Innovation Solution
A flash memory device with a page buffer circuit comprising a main register and a cache register, where the control logic block controls the main register's operation to extend beyond the data transfer period, ensuring non-coincidence of initialization noise with data output, thereby maintaining the main register's activation during a delay period after data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the main register is initialized during the cache read operation to transfer data efficiently, then data transfer speed is improved, but noise from power voltage fluctuations degrades channel conditions and causes data errors
Solution Approach 1:
The patent segments the cache read operation into distinct phases: a first cache read operation that transfers data without initiating main register initialization, and a second cache read operation that occurs after the main register is fully initialized. This temporal segmentation separates the high-speed data transfer phase from the noisy initialization phase, allowing both fast data transfer and reliable transmission without overlapping these conflicting operations.
Solution Approach 2:
The patent performs preliminary data transfer in the first cache read operation before the main register initialization noise occurs. By completing the critical data transfer phase beforehand, the system ensures that sensitive data transmission happens during a clean electrical environment, avoiding the harmful effects of subsequent power voltage fluctuations during register initialization.
2Productivity
If the main register initialization is performed concurrently with data output from the cache register, then operational efficiency is improved, but noise overlap degrades channel conditions
Solution Approach 1:
The patent divides the cache read operations into sequential segments: a first operation that handles data transfer from the cache register to external devices, and a second operation that handles subsequent data requests after main register initialization. This segmentation prevents the overlapping of productivity-critical data output with harmful initialization noise, maintaining both operational efficiency and signal integrity.
Solution Approach 2:
The patent rushes through the critical data transfer phase in the first cache read operation before the harmful initialization noise begins. By completing the essential data output quickly and then allowing the main register initialization to proceed during a less critical period, the system maintains high productivity while avoiding noise interference during sensitive operations.
3Measurement precision
If the main register operation is initiated during the cache read data transfer period, then read performance is improved, but data errors occur due to power voltage noise
Solution Approach 1:
The patent segments read operations into a first cache read that achieves high read performance by transferring data without concurrent initialization noise, and a second cache read that occurs after initialization is complete. This segmentation allows the system to achieve measurement precision in the first operation while avoiding the power voltage noise that would otherwise occur during simultaneous main register initialization.
Data Source
AI summary
A flash memory device, related system ad method are disclosed. The memory device includes a memory cell array a page buffer receiving read data, wherein the page buffer includes a main register transferring read data to a cache register during an read operation, and a control logic block controlling operation of the page buffer during the read operation, such that initialization of the main register continuously extends beyond a time period during which read data is transferred from the main register to the cache register.