Flash Memory Page Buffer Controller for Early Latch Release

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Solution Overview

Problem

Existing flash memory chip programming operations face inefficiencies due to errors in data unit selection and delayed release of data latches, leading to system errors and reduced programming speed.

Innovation Solution

The implementation of a flash memory chip with a page buffer and a controller that converts data units into different patterns using binary tables, allowing for efficient programming and verification of cells in batches, and enabling early release of data latches once certain conditions are met.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the controller performs a normal program by selecting data units with specific binary codes, then the programming operation can be completed, but errors occur in data unit selection leading to system errors

Engineering Contradiction:
Improvedata unit selection accuracyVSAvoidprogramming efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The controller performs preliminary conversion of data units from original binary codes to converted binary codes before the actual programming operation. This preliminary action allows the controller to identify and select only the necessary data units for programming, avoiding errors in data unit selection while maintaining programming efficiency. The conversion process prepares the data in advance, enabling accurate selection during the programming phase.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the controller releases data latches later to ensure all data units are written, then data integrity is maintained, but the release time exceeds the early release requirement causing system errors

Engineering Contradiction:
Improvedata latch release timingVSAvoidlatch release delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The controller performs preliminary conversion of data units and identifies which data latches can be released early, before completing the programming of all data units. By converting data units in advance and analyzing the programming requirements, the controller determines that certain latches can be released earlier than traditionally required, thus meeting the early release requirement while maintaining data integrity through the converted binary code system.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If the controller programs cells based on original binary codes, then the programming operation proceeds, but the process is inefficient due to errors in selection and verification

Engineering Contradiction:
Improveprogramming operation efficiencyVSAvoidprogramming accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The controller changes the parameter representation of data units by converting original binary codes to converted binary codes. This parameter transformation allows the controller to efficiently identify and select data units for programming based on the converted codes, which are specifically designed to facilitate accurate selection and verification. The parameter change eliminates selection errors while improving programming operation efficiency.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12340115B2Data preprocessing (DPP) pattern supporting both normal program and early cache release program (ECRP)
Publication Date: 2025.06.24 YANGTZE MEMORY TECH CO LTD
  • US12340115B2 patent drawing
  • US12340115B2 patent drawing
  • US12340115B2 patent drawing

AI summary

In an aspect, a memory device includes page buffers and a controller coupled to the page buffers. Each of the page buffers includes N data latches configured to store data, where N is a positive integer. The controller is configured to receive data that includes data units, wherein each of the data units includes N bits, store the data units in the N data latches, convert the data stored in the N data latches based on a table, and program cells of the memory device based on the converted data. The table include N rows and 2N columns of bits. Bits from column 2N−1+2 to column 2N in Nth row of the table are identical.