Flash Memory Page Buffer Interleaving for Data I/O Speed
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The data input and output processes in flash memory devices are slower compared to erase operations, hindering the overall operating speed of these devices, especially in high-speed semiconductor applications.
Innovation Solution
Implementing page buffers divided into two or more groups, where data I/O operations are executed in an interleaving manner, allowing for simultaneous and alternating data input and output between these groups to enhance speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data input and output processes are executed sequentially in flash memory devices, then the device structure remains simple, but the operating speed is reduced
Solution Approach 1:
The flash memory device divides the page buffers into multiple groups (first page buffer group and second page buffer group), each capable of independent data input and output operations. This segmentation allows parallel processing of data I/O operations, thereby increasing the overall data I/O speed without requiring complete redesign of the entire buffer system.
Solution Approach 2:
The patent introduces an additional dimension of organization by grouping page buffers into multiple independent units that can operate simultaneously. This dimensional change from a single sequential buffer system to a multi-group parallel system enables concurrent data input and output operations, resolving the speed limitation.
2Loss of time
If data input and output operations are performed sequentially, then the control logic remains simple, but the time taken for data I/O increases
Solution Approach 1:
The control signal generation unit is segmented into multiple independent control signal generation units, each responsible for generating control signals for specific page buffer groups. This segmentation enables simultaneous control of multiple page buffer groups, reducing the total time required for data I/O operations.
Solution Approach 2:
The patent implements continuous data I/O operations by allowing the first and second page buffer groups to perform data input and output operations simultaneously without interruption. The control signal generation units continuously generate control signals to maintain uninterrupted data flow, eliminating idle time between operations.
Data Source
AI summary
A flash memory device comprises a memory cell array, an input buffer unit, an output driver unit, first and second page buffer units, and first and second data handling units. The memory cell array includes two or more memory banks. During a data input operation, the first and second data handling units respectively receive first and second input data from the input buffer unit, and transfer the first and second input data to the first and second page buffers alternately after receiving the external address signals. During a data output operation, the first and second data handling units respectively receive first and second output data from the first and second page buffer units, and transfer the first and second input data to the output driver unit alternately after receiving the external address signals, so that the output driver unit outputs the first and second input data to the external device alternately.