Flash Memory Page Buffer Latch for Continuous Reading

The patent divides the page buffer/sensing circuit into two separate latches (L1 and L2), each capable of independently holding and processing data. This segmentation allows one latch to perform array reading while the other performs data output, enabling continuous reading operations without requiring a single large buffer area. The division of functionality between L1 and L2 resolves the contradiction by maintaining high productivity through parallel operations while keeping the total circuit area compact.

The patent applies preliminary action by precharging the bit lines before the reading operation begins. Specifically, the bit lines are precharged to a reference voltage level prior to sensing the memory cell data. This preliminary precharging action stabilizes the bit line voltage, preventing capacitive coupling interference during the subsequent half-page reading operations. The sensing circuit then reads data from one half page while the bit lines remain stable, and subsequently reads from the other half page without interference.

The patent implements continuity of useful action through seamless pipeline operations between L1 and L2 latches. While L1 performs array reading of the next page, L2 simultaneously outputs data to the external interface. This continuous parallel operation ensures that data output keeps pace with high-frequency external clock signals without interruption. The pipeline architecture maintains reading precision because each latch completes its reading operation fully before transitioning to the next phase, ensuring adequate sensing time despite the high-speed output requirements.