Flash Memory Page Buffer Circuit Retry Mechanism
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Solution Overview
Problem
Conventional flash memory devices face inefficiencies in program operations due to the need for data retransmission when a program fails, which increases memory controller buffer capacity requirements and reduces overall performance.
Innovation Solution
A memory system with a page buffer circuit having first and second registers, where control logic manages data transfer between these registers and allows for data output to external devices, enabling program operations to proceed without retransmitting data if a failure occurs, by reloading data from the first register to the second register upon a reload command.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is reloaded from memory controller into cache latch when program operation fails, then program operation can be retried, but data retransmission increases memory controller buffer capacity requirements and reduces overall performance
Solution Approach 1:
The patent applies preliminary action by pre-loading data into the cache latch before the actual program operation. When a program operation fails, the data is already present in the cache latch and can be immediately re-used without requiring retransmission from the memory controller. This preliminary data preparation eliminates the need for time-consuming data retransmission during retry operations.
Solution Approach 2:
The cache latch serves as an intermediary between the memory controller and the main latch. It holds data locally during program operations, allowing the system to retry failed programs without involving the memory controller again. This intermediary structure decouples the retry operation from the memory controller, eliminating buffer capacity requirements and reducing communication overhead.
2Reliability
If data is reloaded from memory controller into cache latch when program operation fails, then program operation can be retried, but data retransmission increases memory controller buffer capacity requirements
Solution Approach 1:
The cache latch acts as an intermediary buffer within the flash memory device itself, eliminating the need for the memory controller to maintain large buffer capacities for data retransmission. By placing the cache latch in the flash memory device, the system localizes the buffering function, reducing the burden on the memory controller's buffer resources.
Solution Approach 2:
The flash memory device performs self-service by maintaining its own cache latch for data storage during program operations. This self-service capability allows the device to handle program retries internally without requiring external support from the memory controller's buffer resources, making the system more autonomous and efficient.
3Productivity
If conventional cache program operation is used with data retransmission on failure, then program operations can be performed, but overall program performance is reduced due to retransmission overhead
Solution Approach 1:
The cache latch serves as an intermediary that simplifies the data transfer process during program retries. Instead of complex retransmission protocols involving the memory controller, the cache latch provides direct, immediate access to the required data, reducing transfer complexity and improving throughput.
Solution Approach 2:
The patent enables continuity of useful action by maintaining data in the cache latch throughout program operations and retries. This continuous data availability eliminates interruptions caused by data retransmission, keeping the program operation pipeline full and improving overall productivity without adding significant complexity.
Data Source
AI summary
A memory device may include a memory cell array, a page buffer circuit, and/or a control logic. The page buffer circuit may include first and second registers and be configured to store data to be programmed in the memory cell array. The control logic may be configured to control the page buffer circuit to reload data stored in the first register into the second register in response to a reload command input if a program operation fails.