Flash Memory Page Buffer Segmentation and Ground Wire Shielding
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Solution Overview
Problem
The existing layout of page buffers/sense circuits in flash memory devices suffers from reduced area efficiency due to increased capacitance coupling between metal wires, leading to potential erroneous operations during data reading and writing, especially as the degree of integration and number of pages increase.
Innovation Solution
The page buffer/sense circuit is rearranged into 2 columns×4 segments within one pitch, with wires connected to adjacent latch circuits positioned to minimize capacitance coupling, using PMOS and NMOS transistors in defined well regions and a specific layout of metal wires that reduces voltage drops and maintains data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration and number of pages are increased, then the storage capacity is improved, but the capacitance coupling between metal wires increases causing erroneous operations
Solution Approach 1:
A ground wire is introduced as an intermediary element positioned between adjacent metal wires carrying different potentials. This ground wire acts as a shield that reduces capacitance coupling between the metal wires, preventing erroneous operations while allowing increased integration density and page count for higher storage capacity.
Solution Approach 2:
The patent acknowledges that increased integration leads to stronger capacitance coupling, but converts this harmful effect into a manageable one by strategically placing ground wires that utilize the coupling effect to maintain stable potentials. The ground wires transform the potential interference into a controlled reference potential, enabling reliable operation at higher integration levels.
2Device complexity
If the page buffer/sense circuit is arranged into 1 column×8 segments, then the layout is simplified, but the area efficiency is reduced and chip size increases
Solution Approach 1:
The page buffer/sense circuit is segmented into 2 columns×4 segments instead of 1 column×8 segments. This re-segmentation allows for more compact spatial arrangement, reducing the overall chip area while maintaining manageable layout complexity through systematic organization of the segmented units.
Solution Approach 2:
The patent transitions from a single-column vertical arrangement (1×8) to a two-column arrangement (2×4), effectively utilizing the horizontal dimension more efficiently. This dimensional change in the layout structure reduces the vertical span required and improves area efficiency without significantly increasing layout complexity.
3Area of stationary object
If metal wires are positioned closer together to increase integration, then the area efficiency is improved, but voltage drops increase due to capacitance coupling
Solution Approach 1:
Ground wires are positioned between metal wires to serve as intermediary shields. These ground wires reduce the capacitive coupling between adjacent metal wires carrying different potentials, thereby minimizing voltage drops and energy loss while allowing the metal wires to be positioned closer together for improved area efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances area efficiency, minimizes errors from capacitance coupling, and allows for the miniaturization of the chip size while ensuring normal operation of sense circuits.
Implementation Method 1
the influence of the coupled capacitance between a metal wire SLR and a metal wire SLS of another latch circuit on the node SLR is minimized
Data Source
AI summary
A semiconductor memory device facilitating an area efficiency of a page buffer/sense circuit and suppressing erroneous operation due to capacitive coupling between wires is provided. The flash memory 100 of the disclosure includes a memory cell array 110 and a page buffer/sense circuit 170. The memory cell array 110 includes a plurality of memory cells. The page buffer/sense circuit 170 holds data read from a page selected by the memory cell array 110 or holds data to be programmed to a page selected by the memory cell array 110. The page buffer/sense circuit 170 is arranged in n columns×m segments within one pitch in a row direction defined by p number of bit lines extending from the memory cell array 110. n is an integer of 2 or more then 2, and m is an integer of 2 or more then 2.