3D Flash Memory Page Buffer Circuit Selective Erase
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Solution Overview
Problem
The increasing number of stacked word lines in three-dimensional flash memory devices leads to increased chip thickness, making it difficult to perform bulk erase operations due to technical requirements of semiconductor packages, which limits the integration density and efficiency of flash memory chips.
Innovation Solution
A memory device that performs an erase operation using a method other than bulk erase, specifically by applying an erase voltage to certain bit lines while keeping others in a floating state, utilizing a page buffer circuit to manage control signals and voltages, allowing for effective erasure without increasing chip thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked word lines is increased to increase integration density, then the integration density is improved, but the chip thickness increases making bulk erase operations difficult
Solution Approach 1:
The bit lines are divided into two groups: first bit lines to which erase voltage is applied, and second bit lines that are placed in floating state. This segmentation allows selective voltage application to perform erase operations in thinner chips with stacked word lines, resolving the contradiction between increased integration density and maintained chip thickness
Solution Approach 2:
Different voltage conditions are applied to different bit lines: first bit lines receive erase voltage while second bit lines are kept floating. This local differentiation enables effective erase operations in the three-dimensional structure without requiring increased chip thickness, thus maintaining both high integration density and acceptable chip thickness
2Productivity
If bulk erase method is used, then erase operation is performed, but chip thickness must be increased which is not feasible due to semiconductor package requirements
Solution Approach 1:
The erase operation is segmented into selective application of erase voltage to first bit lines while placing second bit lines in floating state. This segmented approach enables erase functionality without requiring the uniform thickness increase needed for bulk erase methods, maintaining both erase efficiency and package compatibility
Solution Approach 2:
The voltage parameters of bit lines are changed differently during erase operation: first bit lines are set to erase voltage level while second bit lines are set to floating state. This parameter differentiation enables effective erase operations in thin chips, resolving the contradiction between erase efficiency and chip thickness constraints
Data Source
AI summary
A memory device includes a cell array and a page buffer circuit. The cell array includes a first to fourth cell strings respectively connected to a first to fourth bit lines. The page buffer circuit is configured to apply an erase voltage to the first and third bit lines based on a first control signal during an erase operation for memory cells of the first to fourth cell strings. The page buffer circuit is configured to place the second and fourth bit lines in a floating state based on a second control signal during the erase operation.