Flash Memory Page Buffer Testing with Precharge and Latch Comparison
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Solution Overview
Problem
Flash memory devices require extensive time for testing due to the need to evaluate each column for defective cells, which slows down the overall testing process.
Innovation Solution
A flash memory device with an input/output buffer unit that compares test data with estimated data, using precharge transistors and latches to determine test result signals, allowing for efficient identification of defective columns and reducing the need for additional storage units for test results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional testing methods are used to evaluate each column for defective cells, then testing accuracy is maintained, but testing time increases significantly
Solution Approach 1:
The patent precharges bit lines to a reference voltage level before actual testing begins. This preliminary action establishes a known initial state for all bit lines, enabling faster subsequent testing operations without compromising accuracy. The precharge operation prepares the testing environment in advance, reducing the time required for each individual column evaluation.
Solution Approach 2:
The patent uses page buffers to store and compare test data with reference patterns. Instead of performing complex evaluations for each column individually, the system creates copies of test data in buffer memory and performs parallel comparisons. This copying approach allows multiple columns to be tested simultaneously, dramatically improving testing throughput while maintaining accuracy.
2Reliability
If additional storage units are added to store test results for all pages, then testing completeness is improved, but device complexity increases
Solution Approach 1:
The patent makes the page buffers serve dual functions: they act as both data buffers during normal operation and as storage units for test results during testing mode. This multi-functionality eliminates the need for separate dedicated storage units for test results, reducing device complexity while ensuring complete testing coverage across all pages.
Solution Approach 2:
The testing system uses existing page buffer structures to store and manage test results without requiring external or additional storage resources. The page buffers self-serve the dual purpose of data handling and result storage, making the testing process complete and reliable while avoiding increased device complexity.
3Speed
If page buffers are configured with precharge transistors and latches, then testing speed is improved, but page buffer complexity increases
Solution Approach 1:
The page buffer is divided into functional segments: precharge transistors for voltage initialization, sensing nodes for data detection, and latches for result storage. This segmentation allows each component to perform its specific function efficiently, improving overall testing speed. The modular structure manages complexity by organizing functions into distinct, manageable units rather than a monolithic design.
Data Source
AI summary
A flash memory device and a method of testing the flash memory device are provided. The flash memory device may include a memory cell array including a plurality of bit lines, a control unit configured to output estimated data and an input/output buffer unit including a plurality of page buffers. Each of the plurality of page buffers corresponds to one of the plurality of bit lines in the memory cell array and is configured to read test data programmed in at least a first page of a memory cell array, compare the read-out test data with the estimated data to determine whether the corresponding bit line is in a pass or failure state and output a test result signal. A voltage of the test result signal is maintained when test data of a second page of the memory cell array is read if the corresponding bit line in the first page is in a failure state.