Flash Memory Page Buffer Segmentation for Program Disturbance Control
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Solution Overview
Problem
Existing NAND flash memory devices face the challenge of reducing program disturbance while avoiding an increase in pass disturbance, which occurs when the pass voltage is elevated to mitigate program disturbance.
Innovation Solution
The solution involves dividing the enabling period into multiple sub-periods and having each page buffer connected to multiple bit lines, allowing for differential voltage application to reduce the equivalent total capacitance and increase channel voltage without raising the pass voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the pass voltage is increased to reduce program disturbance, then program disturbance is reduced, but pass disturbance increases
Solution Approach 1:
The enabling period is divided into multiple sub-periods, and the bit lines are divided into multiple groups. Each page buffer drives different groups of bit lines in different sub-periods. This segmentation allows the channel voltage to be boosted during programming while limiting the pass voltage exposure time for non-programmed memory cells, thereby reducing both program disturbance and pass disturbance simultaneously.
Solution Approach 2:
The patent employs periodic switching of page buffers to drive different bit line groups in alternating sub-periods. During odd sub-periods, odd page buffers drive odd-bit-line groups while even page buffers drive even-bit-line groups, and vice versa in even sub-periods. This periodic action ensures that memory cells experience the boosted channel voltage only during their designated programming sub-period, minimizing pass disturbance while achieving program disturbance reduction.
2Reliability
If the pass voltage is increased to reduce program disturbance, then programming reliability is improved, but energy consumption increases
Solution Approach 1:
By segmenting the enabling period into sub-periods and assigning different bit line groups to different page buffers, the patent achieves reliable programming with reduced energy consumption. The channel voltage is boosted only during necessary programming intervals rather than continuously, reducing overall energy usage while maintaining programming reliability through targeted voltage application.
Solution Approach 2:
The periodic switching between sub-periods allows the system to apply boosted channel voltage only when needed for programming, rather than maintaining high pass voltage continuously. This periodic action reduces average energy consumption while ensuring programming reliability is maintained during the active programming sub-periods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces program disturbance without increasing pass disturbance by optimizing the voltage distribution across bit lines, thereby enhancing the programming efficiency of NAND flash memory devices.
Implementation Method 1
reducing an equivalent total capacitance of memory cells... so as to increase a channel voltage
Data Source
AI summary
A flash memory device including a memory array, a row decoder and M page buffers is provided, wherein M is a positive integer. The memory array includes a plurality of memory cells and is electrically connected to a plurality of word lines and a plurality of bit lines. The row decoder drives a specific word line among the word lines during an enabling period. The M page buffers divide the enabling period into N sub-periods, wherein N is an integer greater than 2. Furthermore, the ith, (i+N)th, (i+2N)th, . . . , (i+(M−1)*N)th bit lines are driven by the M page buffers during the ith sub-period, so as to program the memory cells electrically connected to the specific word line, wherein i is an integer and 1≦i≦N.