Flash Memory Page-EXE Sector Erase Algorithm
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Solution Overview
Problem
Conventional methods for erasing sectors of flash memory in built-in self-test (BIST) circuits face challenges in achieving uniform erase threshold levels, leading to over-erase and under-erase conditions, which are difficult to represent and implement, especially in complex ASIC devices.
Innovation Solution
A page-based sector erase algorithm is implemented in BIST circuitry, divided into two phases: the EXE phase, where erase verifications and block erasures are applied until a portion of each page is erased, and the EOE phase, where words are interactively verified and erased until a user-defined percentage of the maximum number of erase operations is attained, ensuring a uniformly representative erase threshold level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional erase methods are used in BIST circuits, then the erase process can be completed, but non-uniform erase threshold levels occur leading to over-erase and under-erase conditions
Solution Approach 1:
The patent divides the flash memory array into multiple pages and further segments each page into blocks. The erase process is applied in stages: first erasing complete pages, then erasing individual blocks within pages that require additional erasure. This segmentation allows different regions to be erased to different depths, preventing uniform over-erase while ensuring all cells reach the required threshold level.
Solution Approach 2:
The patent implements a two-phase periodic erase process. The first phase performs initial page-level erasure across the entire array. The second phase performs targeted block-level erasure only on specific blocks that require additional erasure cycles. This periodic, multi-stage approach ensures uniform minimum erase threshold while avoiding excessive erasure in already-sufficient blocks.
2Reliability
If interactive testing with external test equipment is used, then memory cells can be tested, but significant overhead time is incurred due to tester limitations
Solution Approach 1:
The patent implements built-in self-test (BIST) circuitry within the flash memory device itself. Test pattern generators and response analyzers are integrated into the memory controller, allowing the device to autonomously generate test patterns, apply them to memory cells, and analyze the responses without requiring external automated test equipment. This self-service capability eliminates tester overhead time while maintaining comprehensive testing accuracy.
Solution Approach 2:
The memory controller is designed to perform multiple functions: normal read/write operations, erase operations, and comprehensive self-testing. The same controller circuits that manage data access also generate test patterns and analyze test results. This multi-functionality allows the device to maintain full testing capability while eliminating the need for separate external testing infrastructure, reducing both time and cost.
3Manufacturing precision
If blanket erasure of the entire sector is applied, then all memory cells are erased, but over-erase conditions occur in cells that already reached the threshold level
Solution Approach 1:
The patent applies the principle of local quality by allowing different regions (pages and blocks) of the flash memory array to have different erase states. After initial page-level erasure, the system evaluates each block individually and applies additional erasure only to specific blocks that require it. This localized approach ensures that blocks already meeting the erase threshold are not subjected to unnecessary additional erasure cycles, preventing over-erase damage while maintaining consistency in blocks that need it.
Data Source
AI summary
Methods of performing a sector erase of flash memory devices incorporating built-in self test circuitry are provided. The present invention employs an interactive verification and sector erase algorithm to verify and repeatedly erase the sector until a portion of the groups of each page of the sector are erased or a first maximum number of erase pulses is achieved. The algorithm further includes a word verification and erase operation that sequentially verifies and erases each word of the sector until each word is erased or a second maximum number of erase pulses is achieved. The second maximum number of erase pulses may be based on a function of the first maximum number of erase pulses. The second maximum number of erase pulses may be input to the sector erase algorithm as a multi-bit code. The second maximum number of erase pulses and conversion of the multi-bit code may be based on a binary multiple of the first maximum number of erase pulses.