Flash Memory Page Inversion for Cell-Level Wear Equalization

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Solution Overview

Problem

Conventional flash memory devices experience uneven wear-leveling across memory cells due to the high wear associated with write and erase operations, leading to reduced lifespan, as existing methods primarily focus on block-level wear equalization without considering individual cell differences.

Innovation Solution

A flash memory device and method that employs an inversion determining unit to generate programming pages based on the number of '1's and '0's in data pages or sub-pages, minimizing the number of memory cells changed during operations and reducing wear-leveling stress, using a memory cell array, programming unit, and data verifying unit to restore data pages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If conventional block-level wear equalization is used, then erase operation management is simplified, but individual memory cell wear differences are not addressed leading to uneven wear-leveling

Engineering Contradiction:
Improvewear equalization managementVSAvoidwear-leveling accuracy
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

The patent segments the wear equalization process from block-level to memory cell-level by maintaining separate wear counters for each memory cell within a block. This allows individual tracking and management of wear for each cell, enabling more precise wear equalization while still operating at the block level for erase operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by treating each memory cell individually with its own wear counter, rather than assuming uniform wear across all cells in a block. This enables differentiated wear management strategies for cells with different wear levels, addressing the uneven wear distribution more effectively.

Inventive Principle:
Principle #3Local quality

2Reliability

If more write and erase operations are performed to update data, then data freshness is improved, but memory cell wear increases reducing lifespan

Engineering Contradiction:
Improvedata freshnessVSAvoidmemory cell lifespan
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent performs preliminary wear equalization by proactively managing write and erase operations based on individual cell wear counters before wear becomes critical. This allows the system to distribute wear more evenly across all cells, extending overall memory lifespan while maintaining data freshness through controlled updates.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms by continuously monitoring wear counters for each memory cell and using this information to make intelligent decisions about which cells to update or skip during write operations. This feedback loop allows the system to balance data freshness requirements with wear management, extending memory lifespan.

Inventive Principle:
Principle #23Feedback

3Device complexity

If data is stored in original format, then storage simplicity is maintained, but wear concentration on specific cells increases

Engineering Contradiction:
Improvedata storage simplicityVSAvoidwear distribution uniformity
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent applies inversion by reversing the data bits (0 becomes 1, 1 becomes 0) before writing to memory cells. This inversion strategy, combined with wear-aware selection of target cells, helps distribute wear more uniformly across the memory block while maintaining data integrity through the invertible transformation.

Inventive Principle:
Principle #13The other way round (Inversion)

4Reliability

If all cells in a block are updated during write operations, then data consistency is ensured, but unnecessary wear on already-updated cells increases

Engineering Contradiction:
Improvedata consistencyVSAvoidwear stress
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies partial action by updating only the necessary portion of memory cells during write operations rather than forcing updates to all cells in a block. By using wear counters to identify which cells actually need updating, the system reduces unnecessary wear stress while maintaining data consistency for the updated portion.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8756464B2Flash memory device and flash memory programming method equalizing wear-level
Publication Date: 2014.06.17 KIOXIA CORP
  • US8756464B2 patent drawing
  • US8756464B2 patent drawing
  • US8756464B2 patent drawing

AI summary

Disclosed are a flash memory device and flash memory programming method that equalizes a wear-level. The flash memory device includes a memory cell array, an inversion determining unit to generate a programming page through inverting or not inverting a data page based on a number of ‘1’s and ‘0’s in the data page, a programming unit to store the generated programming page in the memory cell array; and a data verifying unit to read the programming page stored in the memory cell array, to restore the data page from the programming page according to whether an error exists in the read programming page, and to output the restored data page, and thereby can equalize a wear-level of a memory cell.