Flash Memory Page Layout With Inter-Page Reed-Solomon ECC
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile semiconductor memories face challenges with soft errors due to device manufacturing variations, requiring strong error correction capabilities and increased redundant data, while three-dimensional flash memories struggle to secure dedicated pages or blocks for redundant data, limiting error correction in inter-page directions.
Innovation Solution
A memory system that employs a multi-dimensional error correction code using Reed-Solomon codes in both inter-page and intra-page directions, allowing error correction across pages without dedicated redundant pages by distributing parity data within the same block as user data, reducing the need for additional pages or blocks for redundant data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction coding is performed in units of pages with dedicated redundant pages, then error correction capability is improved, but storage efficiency deteriorates due to increased redundant data pages
Solution Approach 1:
The patent merges user data and parity data into the same physical pages, eliminating separate redundant pages. Multiple data frames and parity frames are concatenated to form integrated pages that contain both user information and error correction codes, thereby improving storage efficiency while maintaining error correction capability.
Solution Approach 2:
The patent introduces inter-page error correction as an additional dimension beyond traditional intra-page correction. By performing error correction across multiple pages in the inter-page direction using Reed-Solomon codes, the system achieves enhanced error correction capability without requiring proportional increases in redundant storage space.
2Reliability
If strong error correction is implemented to counteract soft errors, then data integrity is improved, but the number of pages required for redundant data increases
Solution Approach 1:
The patent makes pages serve multiple functions simultaneously. Each page contains both user data frames and parity frames, allowing the same physical page to store both information and error correction codes. This multi-functionality reduces the total number of pages needed for redundant data while maintaining strong error correction capabilities through inter-page coding.
3Quantity of substance
If three-dimensional flash memory structures are used to increase storage capacity, then storage density is improved, but the ability to secure dedicated pages for redundant data deteriorates
Solution Approach 1:
The patent merges user data and parity data into the same physical pages, eliminating separate redundant pages. Multiple data frames and parity frames are concatenated to form integrated pages that contain both user information and error correction codes, thereby improving storage efficiency while maintaining error correction capability.
Solution Approach 2:
The patent introduces inter-page error correction as an additional dimension beyond traditional intra-page correction. By performing error correction across multiple pages in the inter-page direction using Reed-Solomon codes, the system achieves enhanced error correction capability without requiring proportional increases in redundant storage space.
Data Source
AI summary
According to one embodiment, a memory system encodes a plurality of data frames written in the same block in an inter-frame direction and generates first parity data, encodes the first parity data in the inter-frame direction and generates second parity data, generates a plurality of pieces of first frame data by concatenating at least a part of the first or second parity data with each of the plurality of data frames, encodes each of the plurality of pieces of first frame data in an intra-frame direction and generates a plurality of third parity data, and writes a plurality of pieces of second frame data obtained by concatenating each of the plurality of pieces of first frame data and each of the plurality of pieces of third parity data in a plurality of pages in the same block in the non-volatile memory one by one.