Flash Memory Page Mapping for Reduced Charging Wear
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Solution Overview
Problem
Existing charging/discharging control methods for MLC NAND-type flash chips result in frequent charging and discharging, leading to abrasion and a reduced service life due to the sharing of physical memory cells between least significant and most significant bits, making the process inconvenient and inefficient.
Innovation Solution
A method and system that map a physical page to two coupled logic pages, buffer and merge data corresponding to these pages, and perform charging/discharging control to express the voltage state as a numerical value, allowing simultaneous writing to both bits and reducing the need for repeated charging/discharging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If data is written to LSB and MSB separately in sequential order, then the writing process is simple to implement, but the physical memory cell undergoes repeated charging/discharging operations causing abrasion and reduced service life
Solution Approach 1:
The patent buffers write data for both LSB and MSB before performing the actual programming operation. By preparing the data in advance and determining the optimal programming sequence, the system can execute a single charging operation that satisfies both bit requirements, thereby reducing wear on the flash memory cell while maintaining writing simplicity.
Solution Approach 2:
The patent merges the writing operations for LSB and MSB into a single unified programming operation. When both bits require programming, the system combines their charging requirements and executes them simultaneously in one operation rather than sequentially, reducing the total number of charging/discharging cycles and extending flash chip service life.
2Reliability
If data is buffered and merged for simultaneous writing to both bits, then charging/discharging operations are reduced extending service life, but the writing process becomes more complex
Solution Approach 1:
The patent introduces a buffer memory as an intermediary component between the data input interface and the flash memory array. This buffer temporarily stores write data for both LSB and MSB, allowing the system to coordinate and merge programming operations efficiently. The buffer acts as a mediator that simplifies the control logic by decoupling data reception from the actual programming execution.
Solution Approach 2:
The system includes a control unit that automatically determines the optimal programming sequence based on the buffered data states. The control logic self-manages the complexity of coordinating LSB and MSB programming by automatically identifying when merging operations is beneficial and executing the appropriate charging/discharging sequence without requiring complex external control.
3Ease of operation
If sequential writing to LSB then MSB is performed, then the control logic is simple, but repeated charging/discharging occurs reducing erasure times and increasing wear
Solution Approach 1:
The patent employs feedback mechanisms where the control unit continuously monitors the state of buffered data for both LSB and MSB. Based on this feedback, the system dynamically determines the optimal programming sequence and decides whether to merge operations. This feedback-driven approach allows the control logic to maintain simplicity while intelligently optimizing charging/discharging operations to reduce wear and extend erasure duration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach avoids repeated charging/discharging of multi-layer memory cells, reduces wear on the flash chip, and prolongs its service life by ensuring that electrons are charged only once for a predetermined number during data programming.
Implementation Method 1
Each memory cell of an MLC NAND-type flash chip may have four voltage states. Assuming the first voltage state (11) has an electron number of 0, the second voltage state (10) has an electron number of n, the third voltage state (00) has an electron number of 2n, and the fourth voltage state (01) has an electron number of 3n.
Implementation Method 2
When 11 is changed into 10, it needs to be charged with n electrons. When 11 is changed into 01, it needs to be charged with 3n electrons; when 10 is changed into 00, it needs to be charged with n electrons.
Data Source
AI summary
A method comprises steps of mapping a same physical page to two mutually coupled logic pages, one logic page being formed by mapping the least significant bit on the physical page, and the other logic page being formed by mapping the most significant bit on the physical page; buffering write data in a buffer memory, and merging the data, which is corresponding to the two mutually coupled logic pages, in the buffer memory into a piece of data corresponding to the physical page according to the mapping relationship between the physical page and the two mutually coupled logic pages; and performing charging/discharging control for the multi-layer memory cell of the physical page according to the merged data, so that a voltage state of the multi-layer memory cell is expressed as a numerical value of the merged data.