Flash Memory Paired Sectors Parasitic Loading Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Contemporary flash memory devices are inefficient due to operating at large biases and slower read operations, which are limited by parasitic loading from global bit lines to sense amplifiers.
Innovation Solution
The implementation of a flash memory system with paired sectors, where active and inactive memory devices are coupled with sense amplifiers and reference currents, allowing for reduced parasitic loading and optimized voltage control during read operations by using high voltage control systems to manage voltage pumps and bit lines differently for program, erase, and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If flash memory devices use a single array or independent smaller arrays operating at large biases, then the devices can perform read operations, but the efficiency is reduced due to high voltage requirements (1.8V to 5V)
Solution Approach 1:
The memory array is divided into multiple blocks, each block containing memory cells that can be independently accessed. This segmentation allows parallel read operations across multiple blocks, improving overall read efficiency while enabling lower voltage operation by limiting the voltage burden to smaller sub-arrays rather than the entire array
2Speed
If read operations are performed via global bit line to sense amplifier, then data can be read from memory, but the speed is reduced due to increased parasitic loading
Solution Approach 1:
The bit line structure is segmented into local bit lines for each block, which connect to sense amplifiers. This segmentation reduces the total capacitance and parasitic loading on any single bit line compared to a single global bit line spanning the entire array, thereby increasing read operation speed
Solution Approach 2:
Local bit lines act as intermediaries between the memory cells and the sense amplifiers. These local bit lines isolate the sense amplifiers from the large parasitic capacitance of a global bit line, reducing the loading effect and enabling faster sensing operations
Data Source
AI summary
Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations.