Parallel Erase Mode for Flash Memory Block Reliability
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Solution Overview
Problem
Flash memory cells in arrays experience inconsistent erase times and reliability issues due to varying voltage threshold distributions and increased program and erase cycles, leading to potential overstressing of circuits during parallel erase operations.
Innovation Solution
Implementing a flash memory system with a parallel erase mode (PEM) that allows simultaneous erasure of multiple blocks, limited to a predetermined number of operations to prevent overstressing and ensure reliable erase operations, switching to a normal erase mode after reaching the maximum count to maintain circuit integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel erase mode is used to erase multiple blocks simultaneously, then erase time is reduced and productivity is improved, but circuit stress increases and reliability deteriorates
Solution Approach 1:
The patent implements a dynamic erase mode selection mechanism that adapts between parallel erase mode and normal erase mode based on operational conditions. The system transitions from static erase mode to dynamic mode selection, allowing the erase operation to switch between parallel and normal modes to optimize both speed and reliability depending on the specific operational context.
2Loss of time
If parallel erase mode is used for multiple blocks, then erase time is reduced, but circuit overstress and damage risk increase
Solution Approach 1:
The patent changes the operational parameters of the erase circuit by switching between parallel erase mode (higher speed, higher stress) and normal erase mode (lower speed, lower stress). This parameter change allows the system to adjust the erase operation characteristics based on the number of blocks and circuit conditions, reducing harmful stress while maintaining acceptable erase performance.
3Productivity
If multiple blocks are erased simultaneously, then productivity increases, but erase consistency and reliability worsen due to VT distribution variations
Solution Approach 1:
The patent segments the erase operation into different modes: parallel erase mode for erasing multiple blocks simultaneously when consistency requirements are met, and normal erase mode for erasing blocks individually when higher consistency is required. This segmentation allows the system to handle different erase scenarios with appropriate methods, maintaining both productivity and erase consistency.
Data Source
AI summary
A non-volatile memory can have multiple blocks erased in parallel for a relatively few number of erase operations. This saves time for the user in the set-up of the memory because the erase operation is relatively slow. Problems with parallel erase relate to different blocks having different program/erase histories with the result that the blocks with different histories erase differently. Thus, after a predetermined number of erase cycles are performed, the ability to parallel erase is prevented. This is achieved by allowing parallel erasing operations until the predetermined number of erase operations have been counted. After that predetermined number has been reached, a parallel erase mode disable signal is generated to prevent further parallel erase cycles. The count and the predetermined number are maintained in a small block of the non-volatile memory that is inaccessible to the user.