Unified Flash Memory Parameter Table for Search Speed
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Solution Overview
Problem
Conventional serial flash memory management standards, such as JEDEC Standard No. 216, require a 3-stage search process for information retrieval, do not support all memory functions, and do not consider performance differences, leading to inefficiencies and limitations in managing serial flash memories.
Innovation Solution
The introduction of standard integrated information, including a pseudo basic parameter table, an additional parameter table, and a comprehensive command table, allows for simplified memory information structure and unified management across various serial flash memory models, enabling faster search speeds and support for diverse functions and performance optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the conventional SFDP standard is used for managing serial flash memory, then compatibility with existing memory models is maintained, but search speed is reduced due to the required 3-stage search process
Solution Approach 1:
The patent merges the header, parameter header, basic parameter table, sector map parameter table, and basic instruction table into a single integrated parameter table. This consolidation eliminates the need for the 3-stage search process by organizing all memory information in a unified structure that can be accessed directly, thereby improving search speed while reducing process complexity.
Solution Approach 2:
The patent creates a universal parameter table structure that can manage both conventional SFDP-compliant memory models and non-compliant models. This unified approach allows the system to handle diverse memory types through a single interface, eliminating the need for separate search procedures for different memory variants and thus improving overall search efficiency.
2Adaptability or versatility
If the SFDP standard is used, then standardization is achieved, but functional support is restricted as not all memory functions are supported
Solution Approach 1:
The patent extends the parameter table to include entries for all memory functions, including block protection, persistent protection, dynamic protection, and performance parameters. This universal structure maintains compliance with the SFDP standard while adding support for previously unsupported functions, thereby improving adaptability without sacrificing standard compliance.
Solution Approach 2:
The patent segments the parameter table into functional categories (protection functions, performance parameters, operational modes) while maintaining the overall SFDP tree structure. This segmentation allows comprehensive function support to be added systematically while preserving the standardized format that ensures reliability and compliance.
3Productivity
If the SFDP standard is used, then information structure is simplified, but performance optimization is lost as the system operates at a low speed limit
Solution Approach 1:
The patent segments performance information into distinct parameter table entries that specify speed limits for different bus access modes. This allows the system to retrieve and apply appropriate performance parameters directly from the integrated table, enabling optimization of memory operation speed without requiring complex external performance management mechanisms.
4Ease of operation
If separate management methods are used for SFDP-supporting and non-supporting models, then each model can be managed appropriately, but management complexity increases
Solution Approach 1:
The patent creates a universal parameter table structure that can represent both SFDP-compliant and non-compliant memory models within the same framework. By using optional parameter entries and flexible table organization, the system can manage diverse memory models through a single unified interface, greatly simplifying management operations while maintaining broad model compatibility.
Data Source
AI summary
A system on chip includes a memory information read unit and a memory feature setting unit. The memory information read unit is configured to read standard integrated information using a first instruction or read standard information using a second instruction from at least one of the memory and an application image. The memory feature setting unit is configured to set a feature of the memory using the standard integrated information or the standard information. The memory feature setting unit selects all or some of a plurality of bus access modes defined in the standard integrated information or in the standard information and sets a bus access mode of the memory as one or more of the bus access modes.