Flash Memory Parity Coding Across SLC and MLC Blocks
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Solution Overview
Problem
Conventional flash memory systems have a low utilization rate of memory space due to the need to dedicate a significant portion for parity check codes, reducing the effective storage capacity for user data.
Innovation Solution
Implementing a RAID-like error correction code encoding operation in a flash memory apparatus, which classifies data into groups and uses XOR encoding to generate parity check codes, allowing these codes to be efficiently stored and used for error correction across multiple-level-cell blocks, thereby reducing the need for excessive parity check code storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional parity check coding is used in flash memory, then error correction capability is improved, but memory space utilization deteriorates
Solution Approach 1:
The patent divides data into multiple groups (first group, second group, third group) and applies different parity check coding strategies to each segment. Some segments use full parity check codes while others use reduced or no parity check codes, allowing flexible trade-off between error correction capability and storage efficiency across different data portions.
Solution Approach 2:
The patent dynamically adjusts the parity check code length and coding rate based on data characteristics, error probability, and storage requirements. By changing the parameter of parity check code length (from full-length to reduced-length or zero-length), the system optimizes the balance between reliability and storage capacity.
2Reliability
If more parity check codes are stored for error correction, then error correction capability is improved, but effective storage capacity deteriorates
Solution Approach 1:
Instead of applying full parity check coding uniformly to all data, the patent applies partial parity check coding only to specific data groups that require higher error correction capability. This partial action approach ensures adequate error correction for critical data while minimizing the overhead on overall storage capacity.
Solution Approach 2:
The patent uses copy-back mechanisms where parity check information is stored in alternative locations and retrieved when needed for error correction, rather than permanently dedicating storage space to parity check codes. This allows flexible error correction capability without permanent storage overhead.
3Reliability
If parity check codes are programmed into dedicated pages, then error correction is enabled, but data storage flexibility deteriorates
Solution Approach 1:
The patent designs the flash memory system to use the same storage pages for multiple purposes: data storage, parity check code storage, and error correction information storage. By making pages multi-functional and dynamically assignable, the system maintains error correction capability while maximizing storage flexibility and adaptability.
Solution Approach 2:
The patent implements dynamic allocation of storage pages where the function of each page (data vs. parity check) can change based on current operational requirements. This dynamic approach allows the system to adapt between error correction modes and high-capacity storage modes, providing both reliability and flexibility.
Data Source
AI summary
A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.