Flash Memory Parity Layout Using SLC-to-MLC Internal Copy
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Solution Overview
Problem
Conventional flash memory controllers inefficiently utilize memory space by dedicating one eighth of a data block for parity check codes, reducing the effective storage capacity and user experience due to high error rates during programming.
Innovation Solution
Implementing a RAID-like XOR error code encoding operation in a flash memory apparatus, which classifies data into groups and generates parity check codes for single-level-cell blocks, then performs an internal copy to multiple-level-cell blocks to reduce the number of necessary parity check codes and enhance error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flash memory controllers program parity check codes into dedicated memory locations, then error correction capability is improved, but memory space utilization deteriorates
Solution Approach 1:
The patent merges data pages and parity check code pages into the same physical memory blocks. Instead of dedicating separate blocks for parity codes, the system interleaves parity pages with data pages within the same block structure, allowing simultaneous storage of both without requiring additional dedicated space.
Solution Approach 2:
Memory blocks are designed to serve dual purposes: storing both user data and error correction parity codes. The same physical memory infrastructure is used for multiple functions - data storage, parity storage, and error correction operations - eliminating the need for separate dedicated parity blocks.
2Reliability
If one eighth of memory space is allocated for parity check codes, then error correction capability is improved, but effective storage capacity deteriorates
Solution Approach 1:
The patent combines data pages and parity pages within the same memory block structure. By interleaving them at the page level rather than allocating separate blocks, the system achieves error correction capability without sacrificing one eighth of the total storage capacity to dedicated parity blocks.
Solution Approach 2:
The system changes the organizational parameters of memory storage from block-level separation to page-level interleaving. This parameter change allows dynamic allocation where parity pages are distributed among data pages, optimizing the balance between error correction and storage capacity.
Data Source
AI summary
A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.