Flash Memory Parity Placement for Higher Storage Utilization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional flash memory controllers inefficiently use memory space by dedicating a significant portion to parity check codes, reducing the available space for data storage and leading to lower utilization rates.
Innovation Solution
A flash memory apparatus and storage management method that employs RAID-like error code encoding, classifying data into groups, and using XOR error code encoding to generate parity check codes, which are then appropriately programmed into memory locations, allowing for efficient error correction without sacrificing data storage space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flash memory controllers program parity check codes into dedicated memory pages, then error correction capability is improved, but memory utilization rate deteriorates
Solution Approach 1:
The patent merges the functions of data storage and parity check code storage by programming parity check codes into the same memory pages as data. The controller performs XOR operations between multiple data pages to generate parity check codes, which are then stored in the same page alongside the original data, eliminating the need for dedicated parity pages and improving memory utilization while maintaining error correction capability
Solution Approach 2:
The patent makes memory pages universal by enabling them to serve dual purposes: storing both user data and parity check codes simultaneously. The same memory page that would traditionally be dedicated to parity codes can now store data while the generated parity codes are embedded within the same page structure, allowing the memory system to handle both data storage and error correction functions within the same storage space
2Reliability
If more memory space is allocated to parity check codes, then error correction capability is improved, but available data storage space deteriorates
Solution Approach 1:
The patent combines data and parity check codes in the same memory page, so that the same physical space serves both purposes. Instead of allocating separate space for parity codes, the system generates parity codes from existing data pages and stores them within the same page structure, effectively using zero additional space for error correction while maintaining full data storage capacity
Data Source
AI summary
A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.