Flash Memory Parity Programming Without Frequent Block Erase
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Solution Overview
Problem
Existing memory devices face inefficiencies in error protection, particularly in flash memory, where block erases are slow and frequent, and parity data changes often require block erases, leading to undesired loss of error protection.
Innovation Solution
Implementing a method that allows parity data to be programmed in a non-allowed direction without requiring a block erase by generating parity data using a parity generator array to maintain a number of parity data changes below a threshold, enabling multiple changes before a block erase operation, and using multi-level memory cells to store parity and program data efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If block erase operations are performed frequently to maintain error protection, then reliability is improved, but productivity deteriorates due to slow erase speed
Solution Approach 1:
The memory array is divided into multiple sub-arrays, each with its own parity bits stored in separate memory locations. This segmentation allows parity updates to be performed on individual sub-arrays independently, enabling parallel processing and reducing the overall time required for error protection maintenance compared to processing the entire memory block as a single unit.
Solution Approach 2:
The patent changes the state parameter of parity bits from requiring full block erase to allowing direct programming in a non-allowed direction. By modifying the operational parameters to permit programming parity bits without erasing the entire block, the system maintains error protection while dramatically improving programming speed and reducing write amplification.
2Reliability
If parity data is programmed in non-allowed direction requiring block erase, then error protection is maintained, but loss of time increases due to frequent erasures
Solution Approach 1:
Parity bits are generated and updated in advance during programming operations, allowing the error protection data to be prepared before the actual data write is completed. This preliminary generation of parity information ensures that when programming occurs in non-allowed directions, the parity data is already available and can be programmed directly without requiring time-consuming block erase operations.
Solution Approach 2:
Instead of following the conventional approach where programming in non-allowed directions requires erasing first, the patent inverts this requirement by implementing a system where parity bits can be programmed directly in non-allowed directions without erasure. This inversion of the traditional programming paradigm eliminates the time loss associated with frequent erase operations while maintaining error protection integrity.
3Reliability
If block erase is performed to update parity data, then reliability is maintained, but device complexity increases due to coordinated erase operations
Solution Approach 1:
The memory system is segmented into multiple independent sub-arrays with dedicated parity storage locations for each. This segmentation simplifies the control circuitry by allowing independent management of parity bits for each sub-array, eliminating the need for complex coordinated erase operations across the entire memory block. Each sub-array can be managed independently, reducing the overall system complexity.
Solution Approach 2:
The patent introduces an intermediate mechanism where parity bits are stored in dedicated memory locations that are separate from the main data storage areas. This intermediary storage structure for parity information allows for simplified control logic, as the system can directly program or read parity bits without needing to coordinate complex erase operations across the entire memory block, thereby reducing device complexity.
Data Source
AI summary
Subject matter disclosed herein relates to methods and/or apparatuses, such as an apparatus that includes first and second groups of memory cells. The first group of memory cells stores multiple digits of program data per memory cell. The second group of memory cells stores a parity symbol per memory cell. Other apparatuses and/or methods are disclosed.