Flash Memory Data Recovery via Post-Write Parity Verification
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Solution Overview
Problem
As flash memory devices age, their error rate increases, leading to data corruption due to defects in word-lines, which are difficult to detect and correct, especially as device sizes scale down, resulting in potential data loss and performance degradation.
Innovation Solution
A method is introduced where a data page and its parity data are managed in buffers, allowing for post-write verification to correct errors by reconstructing incorrect pages using parity data and other correctly read pages, reducing the need for extensive controller RAM and enabling robust error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If flash memory devices are scaled down to increase storage density, then storage capacity is improved, but error rate and data corruption increase due to defective word-lines
Solution Approach 1:
The patent applies preliminary action by performing post-write verification after programming data into flash memory. The system verifies written data by comparing it with the original source data and uses parity data to detect and correct errors before the data is considered permanently stored, thus preventing defective word-lines from causing permanent data corruption.
Solution Approach 2:
The patent uses parity data as an intermediary element to detect and correct errors. The parity data is generated from the source data before writing and used during verification to identify corrupted data pages, enabling error correction without requiring additional complex hardware or increasing storage capacity.
2Device complexity
If controller RAM size is reduced to decrease device cost and size, then device complexity is improved, but ability to store and verify data pages during programming is worsened
Solution Approach 1:
The patent extracts the verification function from requiring large controller RAM by separating the verification process into stages. Instead of storing all data pages in controller RAM for verification, the system writes data to flash memory first and then performs verification by reading back and comparing with source data, thus reducing the RAM requirement while maintaining verification capability.
Solution Approach 2:
The patent applies partial action by verifying data in pages rather than requiring all data to be held in RAM simultaneously. The system verifies data page by page or block by block, using only the necessary portion of RAM for current verification operations, thus reducing overall RAM requirements while maintaining comprehensive verification.
3Reliability
If post-write verification is performed to correct errors, then data integrity is improved, but programming time and processing overhead increase
Solution Approach 1:
The patent segments the verification process into efficient stages: generating parity data during the write operation, performing initial verification by comparing written data with source data, and using parity data for error correction only when errors are detected. This segmented approach minimizes the time overhead by avoiding full verification of all data when no errors are present.
Solution Approach 2:
The patent maintains continuity of useful action by integrating parity data generation into the existing write operation flow. The parity data is generated concurrently with data writing rather than as a separate post-processing step, and the verification process reuses the already-written data in flash memory, thus minimizing additional processing time while maintaining continuous productive operation.
Data Source
AI summary
The recovery of data during programming, such as in the case of a broken word-line, is considered. The arrangement described assumes that k pages may be corrupted when the system finishes programming a block. Then these corrupted pages can be recovered using an erasure code. In order to recover any k pages, the system will compute and temporarily store k parity pages in the controller. These k parity pages may be computed on-the-fly as the data pages are received from the host. After programming the block if a problem is detected in a post-write read, and data in up to k pages is corrupt on some bad word-lines, then the missing data is recovered using the k parity pages that are stored in the controller and using the other non-corrupted pages that are read from the block of the memory array and decoded.