Flash Memory Partial Decoder Circuit for Low-Latency Data Recovery

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Solution Overview

Problem

Flash memory devices experience significant latency due to the need for multiple comparisons to determine two-bit binary values from multi-level cells, which affects data storage and access efficiency.

Innovation Solution

Implementing a compaction-based partial decoder circuit and data decoding systems that compact binary values from flash memory cells into fewer bits, using low density parity check codewords and voltage threshold comparisons to generate soft data values, thereby reducing the number of bits required to represent data and enhance transfer efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple voltage threshold comparisons are performed to determine two-bit binary values from multi-level cells, then data storage density is improved, but data access latency increases

Engineering Contradiction:

Improvedata storage densityVSAvoiddata access latency

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The patent segments the data recovery process into distinct phases: voltage threshold comparisons to generate binary values, compaction of binary values to fewer bits, and decoding of the compacted data. This segmentation allows parallel processing of multiple comparisons while reducing overall latency through optimized data flow between stages.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The compaction circuit performs preliminary action by compacting binary values to fewer bits before the decoding stage. This preprocessing step reduces the data volume that subsequent decoding circuits must process, thereby reducing overall access latency while maintaining the high storage density enabled by multi-level cells.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If binary values are compacted to fewer bits, then data transfer efficiency is improved, but system complexity increases

Engineering Contradiction:

Improvedata transfer efficiencyVSAvoiddecoder circuit complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a compaction circuit as an intermediary component between the voltage threshold comparison stage and the decoding stage. This intermediary compacting binary values to fewer bits, simplifying the data that subsequent decoding circuits must process. While this adds a circuit element, it significantly reduces the complexity of the decoding stage and improves overall data transfer efficiency.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Loss of time

If compaction-based decoding is implemented, then data transfer latency is reduced, but manufacturing complexity increases

Engineering Contradiction:

Improvedata transfer latencyVSAvoiddecoder circuit manufacturing

Core Design Contradiction:

Loss of timeVSEase of manufacture

Solution Approach 1:

The compaction circuit is designed with multi-functionality, serving both as a data compression element and as part of the error correction decoding process. This universal design allows the same circuit structure to handle multiple functions, reducing the total number of discrete components needed and simplifying manufacturing while achieving reduced data transfer latency.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9740559B2Systems and methods for compaction based flash memory data recovery

Publication Date: 2017.08.22 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing data to and accessing data from a flash memory.