Flash Memory Peri Region Gate Step Height Reduction
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Solution Overview
Problem
In flash memory devices, the thick polysilicon capping layer in the peri region causes a severe step between the cell and peri regions, leading to degradation of the gate insulating layer and increased leakage current due to impurity infiltration, resulting in reduced yield and well stress failure.
Innovation Solution
A method is developed to fabricate flash memory devices by forming a stack layer with a tunnel insulating layer, charge-trapping layer, blocking oxide layer, and capping conductive layers in both cell and peri regions, with controlled etching and patterning to reduce the step height between regions, using a metal layer and hard mask to form a gate transistor in the peri region, thereby preventing SAC nitride layer degradation during polishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick polysilicon capping layer is formed in the peri region, then the gate insulating layer is protected during fabrication, but a severe step is formed between cell and peri regions causing SAC nitride layer loss and impurity infiltration
Solution Approach 1:
The capping structure is divided into two distinct layers: a first capping conductive layer (thick polysilicon) formed only in the peri region to protect the gate insulating layer, and a second capping conductive layer (thin polysilicon or metal) formed in both cell and peri regions to provide a uniform top surface. This segmentation allows each layer to serve its specific function without compromising the other.
Solution Approach 2:
The first capping conductive layer is selectively formed only in the peri region where the gate insulating layer requires protection, while the second capping conductive layer is formed uniformly across both cell and peri regions. This local quality approach ensures that protection is applied only where needed while maintaining overall surface uniformity.
2Manufacturing precision
If the thick polysilicon layer is removed to reduce step height, then the step between regions is reduced, but the gate insulating layer becomes vulnerable to damage
Solution Approach 1:
The capping structure is divided into two distinct layers: a first capping conductive layer (thick polysilicon) formed only in the peri region to protect the gate insulating layer, and a second capping conductive layer (thin polysilicon or metal) formed in both cell and peri regions to provide a uniform top surface. This segmentation allows each layer to serve its specific function without compromising the other.
Solution Approach 2:
The first capping conductive layer is formed in advance during the stack layer formation process, before subsequent processing steps that would otherwise expose the gate insulating layer to damage. This preliminary protective action ensures the gate insulating layer is safeguarded throughout the fabrication process.
3Ease of manufacture
If the SAC nitride layer is lost during polishing, then the polishing process can proceed, but impurity infiltration occurs degrading the gate insulating layer
Solution Approach 1:
The second capping conductive layer is formed as a protective cushion layer that prevents the loss of SAC nitride layer during the polishing process. This layer acts as a buffer that absorbs the mechanical stress of polishing, thereby protecting the underlying gate structure from impurity infiltration while still allowing the polishing process to complete successfully.
4Ease of manufacture
If a uniform capping layer thickness is used across cell and peri regions, then fabrication is simplified, but the gate height in peri region becomes too low causing SAC nitride layer loss
Solution Approach 1:
The capping structure is divided into two distinct layers: a first capping conductive layer (thick polysilicon) formed only in the peri region to protect the gate insulating layer, and a second capping conductive layer (thin polysilicon or metal) formed in both cell and peri regions to provide a uniform top surface. This segmentation allows each layer to serve its specific function without compromising the other.
Solution Approach 2:
The first capping conductive layer is selectively formed only in the peri region where additional height is needed to prevent SAC nitride layer loss, while the second capping conductive layer is formed uniformly across both cell and peri regions. This local quality approach ensures that height compensation is applied only where needed while maintaining overall process uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the step height between cell and peri region gates, preventing SAC nitride layer loss and impurity infiltration, thereby improving the hump phenomenon and leakage current characteristics of transistors in the peri region, enhancing device yield and performance.
Implementation Method 1
a charge-trapping layer for trapping charges between the gate of a transistor and a channel
Implementation Method 2
The stack layer is etched at a region where a gate will be formed in the peri region, thereby forming a contact hole
Data Source
AI summary
In a method of fabricating a flash memory device, a lower capping conductive layer of a peri region is patterned. A step formed between a cell gate and a gate for a peri region transistor is decreased by controlling a target etch thickness of a hard mask. Thus, an impurity does not infiltrate into the bottom of the gate for the peri region transistor through a lost portion of a SAC nitride layer. Accordingly, a hump phenomenon of the transistor formed in the peri region can be improved. Furthermore, a leakage current characteristic of the transistor formed in the peri region can be improved.