Pipelined Latch Scheme for Flash Memory Clock Tracking
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Solution Overview
Problem
As flash memory devices increase page size to reduce write cycle time, they face challenges in processing command, address, and data signals quickly enough, leading to potential delays and errors due to reduced internal signal setup time margins.
Innovation Solution
The implementation of a pipelined latch scheme that includes command, address, and data latches, coupled to an input latch, allows for serial data to be stored and processed at faster clock rates without delay, using internally generated clock signals to coordinate data movement and latching, ensuring timely processing and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If page size is increased to reduce write cycle time, then productivity is improved, but signal processing capability deteriorates due to reduced internal signal setup time margins
Solution Approach 1:
The patent divides the data processing path into multiple sequential stages: input latch, command latch, address latch, and data latch. Each latch captures signals at different times during the clock cycle, allowing the system to receive faster clock rates while maintaining proper signal setup time margins through staged processing.
Solution Approach 2:
The input latch captures command, address, and data signals before they are fully processed by subsequent latches. This preliminary capture allows the system to prepare signals in advance, enabling faster clock rates while ensuring that all signals are properly set up before being written to the memory array.
2Productivity
If clock rate is increased to reduce write cycle time, then productivity is improved, but internal signal setup time margins deteriorate
Solution Approach 1:
The patent segments the signal processing into multiple latches that operate sequentially. The input latch captures signals early in the clock cycle, and subsequent latches process them in stages. This segmentation allows the clock rate to be increased while maintaining adequate setup time margins at each processing stage.
Solution Approach 2:
The pipelined latch structure enables continuous signal processing throughout the clock cycle. Signals are captured, held, and processed continuously through multiple latches without interruption, allowing the system to operate at higher clock rates while maintaining proper signal setup time margins through uninterrupted processing.
Data Source
AI summary
A flash memory including a first latch having at least one external input to receive at least one command, at least one memory address, and a plurality of data bits, a command decoder coupled to the first latch output; a command latch including a first command latch input, a second command latch input, and a command latch output, the first command latch input to couple to the command decoder output, and the second command latch input to couple to a write command output of an internal clock control generator; and a command register including a first command register input and a second command register input, the first command register input to couple to the command latch output, and the second command register input to couple to an internal latch command output of the internal clock control generator. Additional apparatus, systems, and methods are disclosed.