Flash Memory Planarization Across NVM and Logic Height Steps
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor manufacturing, particularly for flash memory devices, controlling the flatness of underlying layers during lithography operations is challenging due to height differences between non-volatile memory (NVM) cell areas and peripheral logic circuit areas, affecting planarization processes like CMP and etch-back.
Innovation Solution
A method involving the formation of a step between NVM cell and logic circuit areas, followed by additional cleaning operations to remove residual polymers, including plasma cleaning and wet etching, to ensure accurate planarization and prevent defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing operations are performed to planarize the underlying layer, then the flatness of the layer is improved, but height differences between NVM cell areas and logic circuit areas cause manufacturing precision issues
Solution Approach 1:
The substrate is divided into distinct NVM cell areas and logic circuit areas with different topographies. The method segments the manufacturing process into region-specific steps, allowing different areas to be processed according to their unique requirements, thereby managing the complexity of height differences while achieving the desired flatness in each region
Solution Approach 2:
The patent applies local quality by performing selective planarization operations on specific regions. The NVM cell areas and logic circuit areas receive different treatment during CMP and etch-back operations, with the process parameters and sequences tailored to achieve optimal flatness for each local region while accounting for their different height characteristics
2Manufacturing precision
If additional cleaning operations are performed to remove residual polymers, then manufacturing precision is improved, but the complexity of the manufacturing process increases
Solution Approach 1:
The patent applies preliminary action by performing cleaning operations at strategically chosen points in the manufacturing sequence. Plasma cleaning and wet etching are performed before subsequent processing steps to remove residual polymers in advance, preventing contamination from affecting later operations and ensuring accurate planarization results
Solution Approach 2:
The patent uses plasma and wet etching as intermediary cleaning steps between major processing operations. These intermediary cleaning operations remove residual polymers that would otherwise interfere with subsequent steps, acting as mediators that maintain the precision of the overall manufacturing process without requiring complete process redesign
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the yield of semiconductor manufacturing by suppressing defects and improving the planarization process, ensuring better performance and reliability of the semiconductor device.
Implementation Method 1
A plasma cleaning operation is performed
Implementation Method 2
additional cleaning operations to remove residual polymers, including plasma cleaning
Implementation Method 3
wet treatment operation is performed to partially etch the isolation insulating layer in the transition area
Implementation Method 4
additional cleaning operations to remove residual polymers, including plasma cleaning and wet etching
Data Source
AI summary
In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.